Multi-core Processor Shared Cache Partitioning
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Solution Overview
Problem
In multi-core processors, independent caches lead to redundant information storage and reduced bandwidth due to cache coherency algorithms, especially when code and data sets are shared among processor cores, causing inefficiencies in cache management.
Innovation Solution
Implementing a partitioning operating system that temporally and spatially isolates applications and tasks on a shared cache, allowing each processor core to access the cache simultaneously without coherency or arbitration algorithms, thereby eliminating redundant data storage and increasing bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If independent caches are used for each processor core, then cache coherency can be managed, but bandwidth is reduced and cache areas become ineffective due to redundant information storage
Solution Approach 1:
The patent merges multiple independent caches into a single shared cache accessible by multiple processor cores through separate ports. This eliminates redundant information storage across multiple caches while maintaining cache coherency through the shared structure, directly resolving the contradiction between reliability and productivity.
Solution Approach 2:
The shared cache serves multiple processor cores simultaneously through multiple ports, making it a universal resource that can be accessed by any core. This multi-functional design eliminates the need for separate independent caches, reducing redundancy while maintaining coherency and improving bandwidth utilization.
2Adaptability or versatility
If a single cache is arbitrated between multiple processor cores, then cache sharing is achieved, but bandwidth to the cache for a given processor core is reduced by actions of other processor cores
Solution Approach 1:
The patent segments the cache access interface into multiple independent ports, allowing each processor core to access the shared cache simultaneously without arbitration. This segmentation maintains cache sharing capability while eliminating the bandwidth reduction caused by centralized arbitration.
Solution Approach 2:
The patent adds a new dimension to cache access by providing multiple parallel access paths (ports) instead of a single sequential access path. This dimensional change allows simultaneous access from multiple cores, maintaining versatility while dramatically improving bandwidth availability for each core.
3Ease of operation
If independent caches are used, then each processor core has dedicated cache access, but redundant information is stored in multiple caches requiring cache coherency algorithms
Solution Approach 1:
By merging multiple independent caches into a single shared cache structure, the patent eliminates the need for complex cache coherency algorithms. The shared structure inherently maintains consistency, reducing device complexity while preserving dedicated access capabilities through multiple ports.
Data Source
AI summary
A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at least one shared cache simultaneously with another of the plurality of processor cores. Each processor core is assigned one of a unique application or a unique application task and the multi-core processor is operable to execute a partitioning operating system that temporally and spatially isolates each unique application and each unique application task such that each of the plurality of processor cores does not attempt to write to the same address space of the at least one shared cache at the same time as another of the plurality of processor cores.