Shared Cache Power Management via Handshake Registers
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Solution Overview
Problem
Legacy power management units (PMU) in computer systems with shared cache units (SCU) and multiple cores face inefficiencies in power management transitions due to incomplete understanding of the SCU hierarchy, leading to potential slowdowns and increased complexity in design modifications.
Innovation Solution
The implementation of a communication process between compute units and a shared cache unit, facilitated by a power management unit, which reduces the number of interactions and hides the SCU hierarchy, allowing for faster power state transitions by using a shared cache unit handshake register to manage power states and cache flushing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the PMU directly interacts with the SCU to manage power states, then power management can be implemented, but the legacy PMU does not understand the SCU hierarchy leading to incomplete or ineffectual power management
Solution Approach 1:
The patent introduces compute unit handshake registers as intermediary components between the PMU and SCU. These registers act as mediators that enable the legacy PMU to manage SCU power states without requiring the PMU to understand the SCU hierarchy. The handshake registers translate PMU power management requests into SCU-specific operations, resolving the incompatibility between legacy PMU designs and modern hierarchical cache architectures.
2Reliability
If the PMU reengineers to understand the SCU hierarchy, then complete power management can be achieved, but the task is relatively complicated and increases design complexity
Solution Approach 1:
The patent segments the power management functionality by separating PMU responsibilities from SCU management. Instead of requiring the PMU to understand the entire SCU hierarchy, the system divides power management into discrete, manageable components: the PMU handles high-level power state decisions, while compute unit handshake registers handle SCU-specific operations. This segmentation allows legacy PMUs to work with modern SCU architectures without complex reengineering.
3Reliability
If other elements of the computer system are engineered to aid the PMU in power management of an SCU/multiple cores system, then power management can be improved, but it requires a large number of interactions of possibly long latency which could undesirably slow down power management transitions
Solution Approach 1:
The patent implements preliminary action by having compute units check the shared cache validity bit before attempting to enter low power states. This pre-check ensures that cache data is properly handled before power transitions begin, eliminating the need for lengthy post-transition validation interactions. The handshake register mechanism is also pre-configured to handle SCU operations, reducing latency during actual power management transitions.
4Reliability
If the compute unit flushes caches of all modified data before powering down, then data integrity is maintained, but the process takes time and slows down power management transitions
Solution Approach 1:
The patent applies partial action by flushing only the necessary portions of cache data rather than all modified data. The compute unit checks the shared cache validity bit and selectively flushes only the cache lines that are actually modified and need to be preserved. This selective flushing approach maintains data integrity while significantly reducing the time required for cache management during power transitions.
Data Source
AI summary
We report methods, integrated circuit devices, and fabrication processes relating to power management transitions of multiple compute units sharing a cache. One method includes indicating that a first compute unit of a plurality of compute units of an integrated circuit device is attempting to enter a low power state, determining if the first compute unit is the only compute unit of the plurality in a normal power state, and in response to determining the first compute unit is the only compute unit in the normal power state: saving a state of a shared cache unit of the integrated circuit device, flushing at least a portion of a cache of the shared cache unit, repeating the flushing until either a second compute unit exits the low power state or the cache is completely flushed, and permitting the first compute unit to enter the low power state.