Shared Processor Cache Prefetching for I/O Data Transfer
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Solution Overview
Problem
Current computer system architectures face performance limitations due to the rate of data transfer to I/O devices, which can be improved by enhancing direct memory access mechanisms.
Innovation Solution
A data processing apparatus with a shared processor cache connected to multiple processor cores and a bus controller, enabling direct memory access and prefetching of data from main memory to I/O devices, initiated by processor cores without continuous involvement of the bus controller.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the bus controller continuously manages data transfer from shared processor cache to I/O devices, then data transfer reliability is maintained, but system performance and throughput are limited due to controller bottleneck
Solution Approach 1:
The shared processor cache performs preliminary actions by autonomously prefetching data from main memory to the cache before the bus controller needs to transfer it to I/O devices. This preliminary data preparation eliminates waiting time and allows the bus controller to immediately transfer data when requested, thereby increasing data transfer rate without proportionally increasing controller complexity
Solution Approach 2:
The shared processor cache is empowered to self-service by autonomously managing its own data prefetching operations without continuous bus controller intervention. The cache monitors I/O device data requests and independently fetches required data from main memory, reducing the bus controller's management burden while maintaining transfer reliability through coordinated descriptor-based communication
2Loss of time
If data is transferred directly from main memory to I/O devices without prefetching, then memory bandwidth is conserved, but data transfer latency increases due to direct access overhead
Solution Approach 1:
The system performs preliminary data prefetching from main memory to the shared processor cache before actual I/O transfer is needed. This advance data staging reduces the time required for actual data transfer to I/O devices, as the data is already available in the faster cache memory when transfer is initiated
Solution Approach 2:
The shared processor cache acts as an intermediary buffer between main memory and I/O devices. Data is first transferred to the cache (which has faster access times than main memory), and then transferred to I/O devices when needed. This intermediary approach balances memory bandwidth consumption with transfer latency by utilizing the cache's faster access speed for time-critical transfers
3Productivity
If processor cores continuously monitor and manage data transfer operations, then data transfer accuracy is ensured, but processor throughput decreases due to continuous involvement
Solution Approach 1:
The data transfer management function is extracted from the processor cores and assigned to the shared processor cache. Processor cores simply issue descriptors containing transfer parameters, while the cache autonomously manages the actual data prefetching and transfer coordination. This extraction frees processor cores to focus on computation, improving throughput while maintaining transfer accuracy through the cache's dedicated transfer management
Solution Approach 2:
The shared processor cache provides self-service by autonomously managing data transfer operations based on descriptors received from processor cores. The cache independently monitors transfer status, prefetches data when needed, and coordinates with the bus controller without requiring continuous processor core involvement, thereby improving processor throughput while ensuring transfer reliability through its own monitoring mechanisms
Data Source
AI summary
A data processing apparatus is provided, which includes: a plurality of processor cores; a shared processor cache, the shared processor cache being connected to each of the processor cores and to a main memory; a bus controller, the bus controller being connected to the shared processor cache and performing, in response to receiving a descriptor sent by one of the processor cores, a transfer of requested data indicated by the descriptor from the shared processor cache to an input/output (I/O) device; a bus unit, the bus unit being connected to the bus controller and transferring data to/from the I/O device; wherein the shared processor cache includes means for prefetching the requested data from the shared processor cache or main memory by performing a direct memory access in response to receiving a descriptor from the one of the processor cores.