Shared Cache Trigger Control for Multicore Memory Throughput
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Solution Overview
Problem
In multi-core coherent systems, the varying cache structures and memory access characteristics among different processor components lead to increased CPU stall overhead and reduced memory throughput, making it challenging to maintain data consistency and maximize shared memory bandwidth.
Innovation Solution
A multi-core processing system with a memory controller featuring trigger control channels that receive configuration information to detect specific events and trigger memory management commands, optimizing memory access and arbitration to reduce CPU stall overhead and enhance memory throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interconnect handles memory accesses in a serial fashion to guarantee atomicity and data consistency, then data coherency is maintained, but the interconnect becomes the access bottleneck reducing memory throughput
Solution Approach 1:
The patent segments the memory access handling into multiple parallel interconnect channels (first interconnect channel and second interconnect channel). Different types of memory accesses are routed through different channels: critical line first accesses use the first channel while non-critical line fills use the second channel. This segmentation allows simultaneous processing of multiple memory operations, eliminating the serial bottleneck while maintaining data consistency through controlled arbitration in each channel.
2Loss of time
If the lower level memory hierarchy returns the critical line first to un-stall the CPU, then CPU stall overhead is reduced, but the other CPU's stall overhead is extended and shared memory throughput is reduced
Solution Approach 1:
The patent divides memory access requests into two segments: critical line first requests and non-critical line fill requests. Critical requests are routed through the first interconnect channel to quickly un-stall the CPU, while non-critical requests use the second interconnect channel. This segmentation allows the system to satisfy CPU stall requirements without blocking other memory operations, thereby maintaining shared memory throughput.
Solution Approach 2:
The patent introduces a memory controller as an intermediary that arbitrates between multiple memory masters and manages the trigger control channels. The memory controller receives memory management commands, stores them, detects triggering events, and triggers appropriate commands through different interconnect channels. This intermediary coordinates access from multiple CPUs, ensuring that critical line first requests are handled promptly while non-critical requests are processed without interfering with shared memory throughput.
3Adaptability or versatility
If multiple processor components access shared memory resources with different cache structures and access characteristics, then system functionality is enhanced, but CPU stall overhead increases and memory throughput is reduced
Solution Approach 1:
The patent segments memory access traffic based on its characteristics and requirements. Different interconnect channels are assigned to handle different types of accesses: one channel handles critical line first requests from processors with specific cache structures, while another channel handles non-critical line fill requests. This segmentation allows the system to accommodate diverse processor components with different cache structures without their access patterns interfering with each other, thereby maintaining high memory throughput despite enhanced system functionality.
Data Source
AI summary
Techniques including receiving configuration information for a trigger control channel of the one or more trigger control channels, the configuration information defining a first one or more triggering events, receiving a first memory management command, store the first memory management command, detecting a first one or more triggering events, and triggering the stored first memory management command based on the detected first one or more triggering events.