Shared Cache Way Allocation via Source-Specific Segmentation
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Solution Overview
Problem
Modern computing systems face performance degradation due to uneven memory latency across sources in shared cache memory, where one source, such as an I/O device, can occupy significant cache space, leading to undesirable evictions of data from other sources like processor cores, as existing allocation strategies do not distinguish between different sources.
Innovation Solution
A shared cache controller is configured to enable or disable cache fill line allocation separately for each source based on the source of the memory request, using configuration and status registers to manage allocation and create a pseudo-RAM structure, thereby reducing cache size during power-down while maintaining operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If typical cache implementations allow the Least Recently Used (LRU) way within a chosen set to be replaced for allocation, then cache space can be utilized, but one source (e.g., I/O source) can occupy a significant portion of the ways in the cache, leading to undesirable evictions of data from other sources (e.g., processor cores)
Solution Approach 1:
The patent segments the cache ways into multiple groups, where each group is associated with a specific source (e.g., processor core, I/O device, GPU). The cache controller is configured to allocate cache fill lines to specific groups based on the source of the memory request. This segmentation prevents any single source from occupying all cache ways, thereby resolving the contradiction between cache space utilization and data eviction control.
2Adaptability or versatility
If a set-associative shared cache is utilized for data storage by multiple sources (processor cores, GPU, I/O devices), then storage resources are shared, but the system performance degradation from increased average memory latency is not equal for each source
Solution Approach 1:
The patent implements local quality by associating specific cache way groups with specific sources. Each source has preferential access to its associated cache ways, ensuring that data from critical sources (e.g., processor cores) experiences lower latency. This localized quality of service resolves the contradiction between cache sharing capability and system performance by providing differentiated access quality to different sources.
3Quantity of substance
If cache fill line allocation is enabled for all sources, then cache memory is fully utilized, but undesirable evictions occur when one source occupies significant cache space
Solution Approach 1:
The patent segments cache ways into source-specific groups and configures the cache controller to allocate fill lines only to appropriate groups based on request source. This segmentation maintains high cache utilization while preventing any single source from monopolizing cache space, thereby eliminating undesirable evictions of data from other sources.
Data Source
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AI summary
A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.