Shared CAM Address Mapping for 3D NAND Firmware Repair
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Solution Overview
Problem
The challenge of efficiently repairing firmware for multi-plane read operations in 3D NAND memory devices without increasing manufacturing costs due to the need for multiple content addressable memories (CAMs).
Innovation Solution
A content addressable memory (CAM) design with a set of registers, comparators, and multiplexers that facilitate efficient firmware repair by comparing old addresses with input signals and generating output signals for multi-plane read operations, using a shared control circuit for multiple memory planes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple CAMs are used to support multi-plane read operations, then firmware repair capability is improved, but manufacturing cost increases
Solution Approach 1:
A single CAM is designed to serve multiple memory planes through shared control circuitry and configurable address mapping. The CAM can be dynamically allocated to different planes based on operational needs, allowing one CAM to perform the firmware repair function for N memory planes instead of requiring N separate CAMs, thereby reducing manufacturing cost while maintaining repair capability
Solution Approach 2:
The patent combines the firmware repair functionality for multiple memory planes into a single unified CAM structure. By merging the address comparison and mapping functions into one shared CAM resource, the system eliminates the need for multiple separate CAM units, reducing overall component count and manufacturing complexity while preserving the ability to repair firmware across all planes
2Ease of manufacture
If a single CAM is shared across multiple memory planes, then manufacturing cost is reduced, but operational efficiency may be compromised
Solution Approach 1:
The CAM allocation is made dynamic rather than static. The single CAM can be flexibly assigned to different memory planes based on real-time operational requirements and defect patterns. This dynamic configurability allows the system to optimize performance by activating the CAM only when needed for specific planes, minimizing interference with normal operations while maintaining repair capabilities
Solution Approach 2:
The CAM operation is segmented into discrete, controllable units that can be independently activated for different memory planes. The control circuitry can selectively enable the CAM for specific plane operations, allowing parallel processing where the CAM serves one plane at a time without blocking other planes from normal read operations, thus maintaining overall system productivity
Data Source
AI summary
The present disclosure provides a content addressable memory (CAM). The CAM includes a CAM register configured to store a mapping table, N comparators coupling to the CAM register, and N multiplexers coupling to the N comparators respectively and to the CAM register. The mapping table includes first addresses and second addresses. Each one of the first addresses corresponds to one of the second addresses. Each of the N comparators is configured to compare the first addresses with one of N input signals, where N is an integer greater than 1. The N input signals come from N microcontroller units. The N multiplexers is configured to generate N output signals. At least one of the N output signals is obtained according to the mapping table and a comparison output by one comparator of the N comparators.