Shared-Capacitor ADC Architecture for Lower Area and Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional analog-to-digital converters (ADCs) are large in area and high in power consumption, making them inefficient for high-throughput applications that require medium resolution and low latency.
Innovation Solution
The proposed solution involves a novel ADC architecture that reuses the holding capacitor of the track-and-hold amplifier (THA) stage for MDAC operation, allowing for area and power savings by eliminating one charge transfer event and reducing sampling noise, and can be implemented in both single-ended and differential configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional ADC architectures are used, then high throughput and medium resolution are achieved, but large area and high power consumption occur
Solution Approach 1:
The patent merges the THA holding capacitor and MDAC sampling capacitor into a single shared capacitor structure. The holding capacitor of the THA stage is simultaneously used as the sampling capacitor for the MDAC stage, eliminating the need for separate capacitors and reducing overall circuit area while maintaining high throughput performance
Solution Approach 2:
The patent makes the holding capacitor serve dual functions: it acts as the holding capacitor for the THA stage during the track-and-hold phase, and simultaneously serves as the sampling capacitor for the MDAC stage during the conversion phase. This multi-functionality reduces the total number of capacitors needed in the ADC architecture
2Productivity
If conventional ADC architectures are used, then high throughput and medium resolution are achieved, but high power consumption occurs
Solution Approach 1:
The patent combines the THA and MDAC stages into an integrated structure where the holding capacitor is shared between both stages. This merging reduces the total number of active components and charge transfer operations, thereby reducing dynamic power consumption while maintaining the high throughput capability
Solution Approach 2:
The patent extracts and eliminates redundant charge transfer events by directly using the held voltage on the shared capacitor for MDAC conversion. By removing unnecessary intermediate charge transfer steps, the patent reduces dynamic power consumption associated with charging and discharging multiple separate capacitors
3Reliability
If separate THA and MDAC stages are used, then proper signal holding and conversion are achieved, but increased area and complexity result
Solution Approach 1:
The patent merges the THA and MDAC stages into a unified structure where the holding capacitor is shared. This integration maintains the functional separation needed for accurate signal holding and conversion while reducing architectural complexity and the total number of components
Data Source
AI summary
The present invention relates generally to analog-to-digital converters (ADCs). Embodiments of the present invention provide novel ADC architectures directed at reducing the overall ADC area and power consumption. Embodiments of the present invention may be used in pipelined ADCs, cyclic ADCs, and successive approximation (SAR) ADCs, for example. Further, embodiments of the present invention may be implemented using both single-ended and differential configurations.