Shared Capacitor ADC Integration Circuit for Noise-Tolerant Sampling
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Solution Overview
Problem
Traditional touch panel sample and hold (S/H) circuits face saturation issues due to instantaneous noise and pulse overlap problems, particularly in high-frequency applications, leading to inefficiencies and potential disorder in S/H operations.
Innovation Solution
A multi-stage S/H circuit design that shares common capacitors with the SAR-ADC, utilizing a first and second capacitor array module for integration and conversion, respectively, to alleviate saturation and pulse overlap issues by sampling and holding signals in multiple stages and converting them efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional S/H circuits use single-stage sampling with capacitors, then the circuit structure is simple, but the circuit saturates due to large instantaneous noise
Solution Approach 1:
The patent divides the single-stage S/H circuit into multiple stages (first S/H circuit and second S/H circuit). The first stage performs initial sampling and the second stage performs subsequent sampling, allowing the system to recover from noise-induced saturation by discarding only the saturated sample and continuing with subsequent samples, thereby improving reliability without significantly increasing overall complexity.
Solution Approach 2:
The first S/H circuit performs preliminary sampling before the second S/H circuit. This preliminary action allows the system to detect saturation conditions early and discard those samples, preventing them from affecting the final measurement accuracy while maintaining continuous operation.
2Device complexity
If S/H circuits operate only in positive or negative pulses, then the circuit design is simple, but 50% of clock cycles are wasted
Solution Approach 1:
The patent makes the S/H circuit dynamic by enabling it to operate in both positive and negative pulse modes through a control mechanism. The circuit can switch between sampling during positive pulses and negative pulses, allowing full utilization of clock cycles and doubling the effective sampling rate without requiring a completely redesigned circuit architecture.
Solution Approach 2:
The patent implements periodic switching between positive and negative pulse operation modes. By alternating the sampling operation to occur during both positive and negative half-cycles of the clock signal, the system achieves continuous utilization of the clock resource, transforming the wasted 50% of cycles into productive sampling opportunities.
3Adaptability or versatility
If inverters are used to enable operation in both positive and negative pulses, then the S/H circuit can operate in both pulse types, but transmission time delays cause pulse overlap in high-speed circuits
Solution Approach 1:
The patent removes the inverter component from the signal path that causes transmission delays. Instead of using an inverter to generate the complementary clock signal, the design directly utilizes the original clock signal and its inverted version (generated without additional delay-causing inverters in the critical path) to control the sampling switches, thereby eliminating the source of pulse overlap while maintaining the ability to operate in both pulse modes.
Solution Approach 2:
The patent introduces a control mechanism that acts as an intermediary to coordinate the switching between positive and negative pulse modes. This mediator manages the timing and control signals to ensure that sampling operations in both modes are properly synchronized without requiring additional inverters in the critical signal path, thus avoiding pulse overlap while maintaining versatility.
4Reliability
If capacitors are dedicated to S/H circuit only, then the S/H operation is independent, but the die area is large increasing manufacture cost
Solution Approach 1:
The patent merges the capacitor resources between the S/H circuit and the SAR-ADC by using the same capacitor array for both sampling/holding operations and ADC conversion operations. The capacitors serve dual purposes: storing sampled voltages during S/H operation and performing binary weighted summation during ADC conversion, thereby reducing die area while maintaining functional independence through time-division multiplexing and independent control mechanisms.
Solution Approach 2:
The patent makes the capacitor array universal by enabling it to perform multiple functions: it acts as the holding capacitor for the S/H circuit during sampling phases and as the DAC capacitor array for the SAR-ADC during conversion phases. This multi-functionality is achieved through independent control switches and timing mechanisms that allow the same physical capacitors to be selectively connected to different circuit nodes based on the operational phase, significantly reducing the total capacitor count and die area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces the impact of instantaneous noise and pulse overlap, improving the tolerance to noise and reducing the operational inefficiencies in S/H circuits, allowing for more accurate and reliable sensing values to be obtained.
Implementation Method 1
The capacitor array module (520) comprises a plurality of capacitors (520C). The OP amplifier and the capacitor array module form an integration circuit, wherein the integration circuit integrates an analog signal
Implementation Method 2
The OP amplifier and the capacitor array module form an integration circuit
Implementation Method 3
a converter module, configured to convert the output of the capacitor array module to a digital signal
Data Source
AI summary
The present invention provides an integration and analog to digital conversion circuit sharing common capacitors. The circuit comprises a first capacitor array module, a second capacitor module, an integration circuit, an analog to digital conversion (ADC) logic. The first capacitor array module has a plurality of capacitors. The second capacitor array module has a plurality of capacitors. The integration circuit is configured to integrate an analog signal by said first or said second capacitor array module. The ADC logic is configured to convert the output of said first or said second capacitor array module to a digital signal. The ADC logic performs conversion by said first capacitor array module while said integration circuit performs integration by said second capacitor array module, and said ADC logic performs conversion by said second capacitor array module while said integration circuit performs integration by said first capacitor array module.