Shared Capacitor ADC Circuit for Noise-Tolerant Touch Sensing
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Solution Overview
Problem
Traditional touch panel sample and hold (S/H) circuits face saturation issues due to instantaneous noise and pulse overlap problems, particularly in high-frequency applications, leading to inefficiencies and potential disorder in S/H operations.
Innovation Solution
A multi-stage S/H circuit design that shares capacitors with the SAR-ADC, utilizing a capacitor array module, OP amplifier, comparator, and control logic to integrate and convert analog signals, effectively addressing saturation and pulse overlap by sampling and holding signals in multiple stages and canceling noise through differential processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional S/H circuits operate only in positive or negative pulses, then the circuit design is simple, but 50% of clock cycles are wasted
Solution Approach 1:
The S/H circuit is designed to handle both positive and negative pulses through a unified architecture. The circuit uses differential processing with two parallel paths (one for positive pulses, one for negative pulses) that share common components including the capacitor array, OP amplifier, and control logic, enabling the same circuit to perform sampling and holding operations for both pulse types without wasting clock cycles
Solution Approach 2:
The patent merges the previously separate positive-pulse and negative-pulse processing paths into a single integrated circuit. By combining the capacitor arrays, OP amplifiers, and control logic into a shared infrastructure with differential operation, the design achieves full clock cycle utilization while maintaining manageable complexity through component sharing
2Productivity
If inverters are used to enable operation in both positive and negative pulses, then the S/H circuit can utilize both pulse types, but transmission time delays cause pulse overlap in high-speed circuits
Solution Approach 1:
The patent removes the inverter component from the signal path entirely. Instead of converting negative pulses to positive through inversion (which introduces delay), the design directly processes both positive and negative pulses through differential paths, eliminating the source of transmission time delay and pulse overlap
Solution Approach 2:
The control logic acts as an intelligent intermediary that directly manages the timing and coordination of both positive and negative pulse processing paths without requiring signal inversion. It generates appropriate control signals to switch between paths and ensures proper timing synchronization, avoiding the delay issues associated with inverter-based approaches
3Area of stationary object
If capacitor array is shared between S/H circuit and SAR-ADC, then die area is reduced, but the capacitors must serve dual functions requiring precise timing control
Solution Approach 1:
The patent implements a time-division multiplexing scheme where the shared capacitor array alternates between serving the S/H circuit and the SAR-ADC in periodic cycles. During sampling phases, capacitors are configured for S/H operation; during conversion phases, they are reconfigured for ADC operation. This periodic switching is coordinated by control logic that manages the timing sequences to ensure proper functionality in both modes
Solution Approach 2:
The circuit employs dynamic reconfiguration of the capacitor array through electronically controlled switches that can change the capacitor connections and configurations on-the-fly. This dynamic switching capability allows the same physical capacitors to be adapted for different functions (S/H or ADC) based on the current operational phase, enabling flexible dual-purpose operation without permanent structural changes
4Reliability
If multi-stage S/H circuit is used to reduce noise impact, then noise tolerance increases, but the circuit complexity increases
Solution Approach 1:
The patent divides the S/H operation into multiple stages, with each stage processing a portion of the signal and contributing to the final sampled value. This segmentation allows noise to be distributed and managed across stages rather than overwhelming a single stage, improving noise tolerance through incremental processing while using modular design to manage complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces the impact of instantaneous noise, increases tolerance to noise, and improves operational efficiency by allowing simultaneous sampling and holding of positive and negative pulse cycles, thereby enhancing the accuracy and reliability of touch panel measurements.
Implementation Method 1
The capacitor array module has a plurality of capacitors. The integration circuit is configured to integrate an analog signal by the capacitor array module.
Implementation Method 2
The OP amplifier is configured to receive said input signal and said reference voltage VCM. An output end of said OP amplifier is coupled to said capacitor array module.
Implementation Method 3
The ADC logic is configured to convert the output of the capacitor array module to a digital signal.
Implementation Method 4
A second end of said plurality of capacitors are coupled to a switch. When said control signal is a first signal, said first end and said second end of said plurality of capacitors are connected to said reference voltage.
Data Source
AI summary
The present invention provides an integration and analog to digital conversion circuit sharing common capacitors. The circuit comprises a capacitor array module, an integration circuit, and an analog to digital conversion (ADC) logic. The capacitor array module has a plurality of capacitors. The integration circuit is configured to integrate an analog signal by the capacitor array module. The ADC logic is configured to convert the output of the capacitor array module to a digital signal.