Capacitance-to-Voltage Interface Circuit with Shared Capacitor Bank
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Solution Overview
Problem
Conventional capacitance-to-voltage interface circuits in mobile devices require separate capacitor banks for offset voltage and SAR operations, leading to increased physical size and power consumption, which is undesirable for reducing the integrated circuit die area and battery life.
Innovation Solution
A reconfigurable capacitance-to-voltage interface circuit utilizing a shared capacitor bank for both offset voltage and SAR operations, enabled by a switching architecture that rearranges circuit topologies to support different operational phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate capacitor banks are used for offset voltage and SAR operations, then the circuit can perform both functions independently, but the physical size and power consumption increase
Solution Approach 1:
The patent merges the offset capacitor bank and SAR capacitor bank into a single shared capacitor bank. The switching architecture routes different capacitor elements to different functional nodes (offset node or SAR node) depending on the operational phase, allowing one physical capacitor bank to serve both offset voltage generation and SAR conversion functions independently and sequentially
Solution Approach 2:
The capacitor bank is designed with universal functionality to perform multiple roles: during offset calibration phase, capacitors are connected to provide offset voltage to the amplifier; during SAR conversion phase, the same capacitors are reconfigured to perform binary-weighted charge redistribution for ADC operations. This multi-functionality eliminates the need for separate dedicated capacitor banks
2Reliability
If separate capacitor banks are used for offset voltage and SAR operations, then the circuit can perform both functions independently, but the power consumption increases
Solution Approach 1:
The patent merges the offset capacitor bank and SAR capacitor bank into a single shared capacitor bank. The switching architecture routes different capacitor elements to different functional nodes (offset node or SAR node) depending on the operational phase, allowing one physical capacitor bank to serve both offset voltage generation and SAR conversion functions independently and sequentially
Solution Approach 2:
The circuit operates in periodic phases, alternating between offset calibration phase and SAR conversion phase. During each phase, the switching architecture configures the capacitor bank appropriately for that specific function. This time-division multiplexing allows the same hardware to perform multiple functions sequentially, reducing overall power consumption compared to having always-active separate capacitor banks
3Area of stationary object
If a shared capacitor bank is used for both offset voltage and SAR operations, then the physical size and power consumption are reduced, but the circuit requires reconfigurable switching architecture
Solution Approach 1:
The capacitor bank is designed with dynamic reconfigurability through switching elements that can change the circuit topology based on operational phase. During offset calibration, switches connect capacitors to the amplifier offset node; during SAR conversion, the same switches reconfigure the capacitors into binary-weighted stages connected to the SAR ADC node. This dynamic switching capability allows one physical capacitor bank to assume different functional configurations as needed
Data Source
AI summary
A capacitance-to-voltage interface circuit includes a capacitive sensing circuit, an amplification circuit adapted for selective coupling to the capacitive sensing circuit, a capacitor bank comprising a plurality of binary-weighted capacitors, and a switching architecture associated with the capacitive sensing circuit, the amplification circuit, and the capacitor bank. The switching architecture reconfigures the capacitance-to-voltage interface circuit for operation in a plurality of different phases, including an amplification phase and an analog-to-digital conversion phase. During the amplification phase, the capacitor bank is utilized for offsetting capacitance of the amplification circuit. During the analog-to-digital conversion phase, the capacitor bank is utilized in a successive approximation register.