Shared Capacitor Design for DRAM Cell Scaling
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Solution Overview
Problem
In highly integrated and scaled-down semiconductor devices, such as DRAMs, achieving sufficient electrostatic capacitance in a limited area is challenging due to the inverse proportionality of capacitance to equivalent oxide thickness and the need for larger surface areas and higher dielectric constants.
Innovation Solution
A semiconductor device design where multiple memory cells share a single capacitor, allowing for increased capacitance by optimizing the area and structure of the capacitor, including a honeycomb or zigzag arrangement, and using a shared storage node contact to enhance capacitance without the need for additional landing pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the capacitor size is increased to achieve sufficient electrostatic capacitance, then the capacitance increases, but the device area increases which contradicts the scaling down requirement
Solution Approach 1:
The patent merges two memory cells into a single shared capacitor structure. The first and second capacitors are combined into one capacitor that serves both memory cells, reducing the total capacitor area while maintaining sufficient capacitance for both cells. This is achieved by sharing the capacitor between two transistors and two memory cells, effectively halving the capacitor area requirement per memory cell.
Solution Approach 2:
The patent transitions from a planar capacitor arrangement to a three-dimensional structure by forming the capacitor electrode and plug in vertical layers. The capacitor electrode is formed extending in the third direction (vertical) through the substrate, utilizing the vertical dimension to increase capacitance without proportionally increasing the planar area footprint.
2Reliability
If the equivalent oxide thickness is decreased to increase capacitance, then the capacitance increases, but the manufacturing precision requirement increases
Solution Approach 1:
The patent changes the capacitance enhancement approach from reducing equivalent oxide thickness to increasing the capacitor electrode surface area through vertical extension. Instead of making the dielectric layer thinner (which requires precise thickness control), the patent extends the electrode vertically and increases its surface area, achieving capacitance improvement through geometric parameters that are easier to control manufacturally.
3Reliability
If a larger three dimensional electrode is formed to increase surface area and capacitance, then the capacitance increases, but the device complexity increases
Solution Approach 1:
The patent segments the capacitor formation into distinct fabrication stages: forming the capacitor electrode pattern, forming the capacitor dielectric layer, and forming the capacitor plug. This segmentation allows each component to be optimized and controlled separately, reducing overall device complexity while achieving the three-dimensional electrode structure needed for high capacitance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively increases electrostatic capacitance, simplifies the fabrication process, and improves yield by allowing for a larger capacitor area, thereby addressing the challenges of scaling down while maintaining capacitance.
Implementation Method 1
An electrostatic capacitance of a capacitor is proportional to a surface area of an electrode and a dielectric constant of a dielectric film and is inversely proportional to an equivalent oxide thickness of the dielectric film
Data Source
AI summary
A semiconductor device includes a first memory cell including a first transistor and a first capacitor, the first transistor comprising a first gate electrode, a first source, and a first drain; a second memory cell including a second transistor and the first capacitor, the second transistor comprising a second gate electrode, a second source, and a second drain; a first word line coupled to the first gate electrode; and a second word line coupled to the second gate electrode. The first capacitor is electrically connected between the first and second transistors.