Shared Capacitor Boost Circuit for SRAM Write Reliability
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Solution Overview
Problem
Designing robust SRAMs that can be read and written to across all operational voltage ranges is challenging due to variations in device properties, leading to read and write failures, especially at low voltage operations, and existing solutions like active body-biasing controlled boost transistors result in area overhead and charge leakage.
Innovation Solution
A semiconductor memory storage device with access control circuitry comprising a capacitor and switching circuitry that controls voltage levels on access control lines, allowing for flexible voltage adjustments to facilitate data access, reducing the need for individual circuits for each line and minimizing area overhead while maintaining efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a boost transistor is added per word line to increase voltage for writes, then write ability is improved, but area overhead increases and charge leakage occurs due to additional delay
Solution Approach 1:
Multiple word lines share a common boost circuit instead of each having its own dedicated boost transistor. The shared circuit uses switching elements to selectively connect the boost capacitor to different word lines, reducing the total transistor count and area overhead while maintaining the voltage boosting capability for writes.
Solution Approach 2:
A single boost circuit serves multiple word lines by selectively connecting to different lines through switching elements. This universal circuit performs the write-boosting function for all word lines in the group, eliminating the need for dedicated boost transistors on each line and reducing overall area.
2Reliability
If voltage on word line is increased to facilitate writes, then write ability is improved, but read disturb increases making cells more likely to be corrupted
Solution Approach 1:
The word line voltage is dynamically adjusted based on the operation type (read or write). During writes, the boost circuit increases voltage to ensure proper writing. During reads, the boost is disabled and voltage is kept at normal levels to prevent read disturb. This dynamic control resolves the contradiction by applying high voltage only when necessary for writes.
Solution Approach 2:
The boost circuit operates periodically or selectively based on operation requirements rather than continuously. It activates only during write operations and remains inactive during read operations, providing voltage boosting at the appropriate times to avoid read disturb while maintaining write ability.
3Reliability
If voltage scaling is reduced to maintain write ability, then write reliability is improved, but power consumption increases and device size increases
Solution Approach 1:
The circuit temporarily changes the voltage parameter during write operations by activating the boost circuit to increase word line voltage above the normal operating level. This temporary parameter change enables reliable writes at lower nominal voltages, reducing overall power consumption while maintaining write reliability when needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides improved flexibility and efficiency in voltage control, reducing read and write failures across voltage ranges, and enhances the performance of semiconductor memory by allowing the same device to increase or decrease voltage levels as needed, thereby improving data access and reducing power consumption.
Implementation Method 1
access control circuitry for controlling a voltage level supplied to a selected one of at least two of said access control lines during access to said storage cell, said access control circuitry comprising a capacitor and switching circuitry
Data Source
AI summary
A semiconductor memory storage device is disclosed. This memory device has a plurality of storage cells for storing data; a plurality of access devices for allowing access to the corresponding plurality of storage cells, the plurality of access devices being arranged in at least two groups, each of the at least two groups being controlled by an access control line; access control circuitry for controlling a voltage level supplied to a selected one of at least two of the access control lines during access to the storage cell, the access control circuitry comprising a capacitor and switching circuitry; and control circuitry responsive to a data access request to access a selected storage cell to: connect a selected one of the access control lines to a voltage level to allow access via one of the access devices to the selected storage cell; and to control the switching circuitry of the access control circuitry to connect the capacitor of the access control circuitry to the selected access control line and thereby change the voltage level supplied to the selected access control line.