Shared Carry Gate Driver for Lower Dead Space and Power

Solution Overview

Problem

The integration of a large number of transistors and signal wires in a gate driver within a display device increases dead space and power consumption.

Innovation Solution

A gate driver design that includes a control circuit, node separation transistor, and gate output circuits, where the node separation transistor separates control nodes to control voltage, and the gate output circuits share a common carry output circuit, reducing the number of transistors and signal wires.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the gate driver integrates more transistors and signal wires to provide more gate signals, then the functionality and versatility improve, but the dead space and power consumption increase

Engineering Contradiction:

Improvegate signal output capabilityVSAvoiddead space

Core Design Contradiction:

Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

Multiple gate output circuits share a common control circuit and carry output circuit, merging previously separate functional blocks into a unified structure that provides multiple gate signals while reducing overall transistor and wire count

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The common control circuit and carry output circuit serve multiple gate output circuits simultaneously, enabling one circuit block to perform multiple functions and generate multiple gate signals with different timings

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If the gate driver integrates more transistors and signal wires to provide more gate signals, then the functionality and versatility improve, but the power consumption increases

Engineering Contradiction:

Improvegate signal output capabilityVSAvoidpower consumption

Core Design Contradiction:

Adaptability or versatilityVSUse of energy by stationary object

Solution Approach 1:

Multiple gate output circuits share a common control circuit and carry output circuit, merging previously separate functional blocks into a unified structure that provides multiple gate signals while reducing overall transistor and wire count

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The common control circuit and carry output circuit serve multiple gate output circuits simultaneously, enabling one circuit block to perform multiple functions and generate multiple gate signals with different timings

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Reliability

If the gate driver uses separate control circuits for each gate output circuit, then the control precision and reliability improve, but the device complexity increases

Engineering Contradiction:

Improvecontrol reliabilityVSAvoidcircuit complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Multiple gate output circuits share a common control circuit and carry output circuit, merging previously separate functional blocks into a unified structure that provides multiple gate signals while reducing overall transistor and wire count

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The gate driver is segmented into independent gate output circuits that share common control resources, allowing each gate signal to be controlled independently while utilizing shared infrastructure to reduce overall complexity

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12488766B2Gate driver

Publication Date: 2025.12.02 SAMSUNG DISPLAY CO LTD

AI summary

A gate driver includes a plurality of stages. At least one of the stages includes a control circuit configured to control a first control node in response to a first carry clock signal, a node separation transistor connected between the first control node and a second control node, a carry output circuit configured to output a carry signal in response to a voltage of the second control node, and a plurality of gate output circuits configured to output a plurality of gate signals having different timings in response to the voltage of the second control node.