Shared C-DAC SAR ADC for High-Resolution Image Sensor Columns
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Solution Overview
Problem
High-speed, low-power successive approximation register (SAR) analog-digital converters (ADCs) for CMOS image sensors face challenges in achieving high resolution and small area integration due to the size requirements of the reference voltage generator, which degrades performance when reduced in size to fit within a single column, and the increased area needed for high-resolution ADCs using capacitor digital-to-analog converters (C-DACs).
Innovation Solution
A shared capacitor digital-to-analog converter (C-DAC) is implemented across multiple columns, allowing for efficient generation and distribution of a reference voltage, with an analog-digital conversion mode decision circuit determining whether to perform LSB or full analog-digital conversion based on comparison signals, thereby optimizing the use of shared SAR operation logic, MSB storage, and ranging circuits to reduce area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a reference voltage generator is installed at each column for SAR ADC, then conversion accuracy is improved, but area occupied by ADC increases
Solution Approach 1:
The patent merges the reference voltage generation function from individual column ADCs into a shared circuit that serves multiple columns. The shared reference voltage generator produces reference voltages that are distributed to multiple SAR ADCs across different columns, eliminating the need for separate reference voltage generators at each column while maintaining conversion accuracy.
Solution Approach 2:
The shared reference voltage generator is designed to serve multiple functions and multiple columns simultaneously. It generates reference voltages that can be used by multiple SAR ADCs in different columns, making the reference voltage generation system universal rather than dedicated to a single column, thus reducing overall area.
2Area of stationary object
If the size of reference voltage generator is reduced to fit into one column, then area is reduced, but performance of reference voltage generator and overall SAR ADC performance degrades
Solution Approach 1:
By combining multiple reference voltage generation functions into a single shared circuit that serves multiple columns, the patent achieves better performance than what could be obtained from a reduced-size individual generator. The shared generator can be optimized for performance while its output is distributed to multiple columns, avoiding the performance degradation that would result from miniaturizing individual generators.
3Use of energy by moving object
If C-DAC SAR is used to improve power efficiency and operation speed, then power consumption is reduced, but area of C-DAC is doubled as resolution bit is increased by one bit
Solution Approach 1:
The patent merges the C-DAC functionality across multiple columns by implementing a shared C-DAC that serves multiple SAR ADCs. Instead of each column having its own full-resolution C-DAC, the shared C-DAC is designed to handle the combined requirements, reducing the total capacitor array area while maintaining the power efficiency and speed benefits of C-DAC SAR architecture.
Data Source
AI summary
A successive approximation register (SAR) analog-digital converter (ADC) may include a comparison circuit coupled to an array of pixels arranged in rows and columns to receive a first pixel signal and a second pixel signal from a first column and a second column, respectively, and structured to compare each of the first and second pixel signals with a reference voltage and output comparison signals; an analog-digital conversion mode decision circuit located to receive the comparison signals from the comparison circuit and structure to provide a mode decision value which decides an analog-digital conversion mode out of different analog-digital conversion modes based on the comparison signals from the comparison circuit; and a shared circuit shared by the first and second columns, and structured to generate the reference voltage based on the comparison signals from the comparison circuit and the mode decision value from the analog-digital conversion mode decision circuit, the shared circuit outputting the reference voltage to the comparison circuit.