Shared CDR Signaling Across MCM Lanes for Phase Alignment
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Solution Overview
Problem
In Multi-Chip-Modules (MCMs), conventional Clock-Data-Recovery (CDR) circuits are power and area intensive, especially when multiple lanes require phase alignment, leading to significant additional power and area consumption.
Innovation Solution
Implementing a configuration where a single CDR circuit is used for clock and data restoration on one lane, with other lanes utilizing simpler samplers that receive phase correction signaling to adjust sampling phases, reducing the need for full CDRs and thus saving power and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional CDR circuits are used for each lane in MCMs, then phase alignment and clock data recovery are achieved, but power consumption and area usage increase significantly
Solution Approach 1:
The patent merges the CDR functionality into a single shared circuit that serves multiple lanes. Instead of having separate CDR circuits for each lane, one CDR circuit recovers the clock signal and generates phase correction signals that are applied to multiple samplers across multiple lanes, thereby achieving phase alignment while reducing power consumption and area usage.
Solution Approach 2:
The shared CDR circuit performs multiple functions: it recovers the clock signal from one lane and simultaneously generates phase correction signals for multiple other lanes. This multi-functional approach allows a single circuit to serve multiple purposes across different data lanes, reducing the overall number of circuits needed.
2Reliability
If conventional CDR circuits are used for each lane in MCMs, then clock data recovery is achieved, but area usage increases significantly
Solution Approach 1:
The patent combines the clock data recovery functionality into a single shared CDR circuit that serves multiple lanes. The recovered clock and generated phase correction signals are distributed to multiple samplers, eliminating the need for separate CDR circuits in each lane and thereby reducing area usage.
Solution Approach 2:
The patent segments the CDR functionality into a dedicated shared recovery circuit and multiple simpler sampler circuits. The complex clock recovery and phase correction generation is performed once in the shared circuit, while each lane uses a simpler sampler that applies the shared phase correction signals, dividing the system into functionally distinct segments.
3Use of energy by moving object
If a single CDR circuit is used for multiple lanes, then power and area are saved, but phase alignment across lanes must be maintained
Solution Approach 1:
The shared CDR circuit uses feedback mechanisms to monitor the phase alignment across multiple lanes and dynamically adjusts the phase correction signals accordingly. This feedback ensures that even with a single shared CDR circuit, proper phase alignment is maintained across all lanes by continuously adapting the correction signals based on observed phase differences.
Data Source
AI summary
A Multi-Chip-Module (MCM) includes an MCM substrate, and at least a data producing IC (DPIC) and a data-consuming IC (DCIC), both mounted on the MCM substrate and connected to one another through a high-speed bus including at least first and second embedded-clock data lanes. The DCIC includes a clock-data recovery circuit (CDR) and a data sampler. The CDR is configured to restore a data and a clock from the first data lane, and to output phase correction signaling. The data sampler is configured to restore the data from the second data lane by sampling the second data lane at a phase responsive to the phase correction signaling derived from the first data lane.