Shared Clock Data Recovery With Transition Detection for Multi-Channel Links
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Solution Overview
Problem
Current clock data recovery units in high-speed parallel link systems face challenges in recovering robust clock signals due to inter-symbol interference (ISI) and crosstalk-induced jitter (CIJ), leading to increased chip area and power consumption, as well as limitations in detecting specific time points of transitions.
Innovation Solution
A transition detector is designed to recover clock signals by using phase correctors to generate compensation clock signals and integrators to detect transitions based on training pattern signals, with comparators and mode signal maintaining units to ensure accurate detection and minimize interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clock data recovery units are used for multiple channels, then clock signal recovery capability is improved, but chip area and power consumption increase
Solution Approach 1:
The patent merges multiple clock data recovery functions into a single shared unit. The CDR unit is configured to sequentially process multiple channels by switching between them using a channel selection signal, eliminating the need for separate CDR units for each channel while maintaining recovery capability across all channels.
Solution Approach 2:
The single CDR unit is designed with multi-functionality to handle multiple channels. It includes a phase corrector and transition detector that can operate on different channels by receiving control signals, allowing one unit to perform the work of multiple dedicated units.
2Ease of manufacture
If digital data is used for transition detection, then detection simplicity is improved, but detection precision of specific time points deteriorates
Solution Approach 1:
The patent introduces an analog hold signal as an intermediary between the digital data signal and the transition detection process. The hold signal is generated by holding the analog data signal at its maximum and minimum levels, providing clear transition points that improve detection precision while maintaining compatibility with digital processing.
Solution Approach 2:
The system performs preliminary processing by generating the hold signal before transition detection. This hold signal preparation step pre-establishes clear voltage levels that make subsequent transition detection more precise, allowing the detector to identify exact transition time points rather than relying solely on digital sampling.
Data Source
AI summary
A clock data recovery unit includes: a phase corrector generating a first compensation clock signal and a second compensation clock signal based on an external clock signal; and a transition detector, wherein the transition detector comprises: a first integrator configured to integrate a first training pattern signal according to the first compensation clock signal to provide a first integration signal; and a second integrator configured to integrate the first training pattern signal according to the second compensation clock signal to provide a second integration signal, wherein, in response to the first integration signal being greater than a first reference voltage and the second integration signal being less than the first reference voltage, occurrence of a transition of the first training pattern signal is detected.