Shared CDR Receiver Architecture for Multi-Scheme Video Signals
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Solution Overview
Problem
Receivers designed to support multiple transmission schemes for high-definition video signals face increased circuit size, leading to larger semiconductor chips and higher manufacturing costs.
Innovation Solution
A receiver architecture that includes a phase-locked loop (PLL) circuit for generating an internal clock, a demodulator for processing modulated signals, and a selector to choose between baseband and demodulated signals, allowing a single clock data recovery (CDR) circuit to process both, thereby reducing the overall circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a receiver supports multiple transmission schemes (baseband and modulated signals), then the receiver's functionality and adaptability are improved, but the circuit size and device complexity increase
Solution Approach 1:
The CDR circuit is designed to perform multiple functions by selectively processing either baseband signals or demodulated signals. The selector switches between these two signal types, allowing a single CDR circuit to handle both transmission schemes (HDMI and wireless HD) without requiring separate dedicated circuits for each scheme, thereby reducing overall device complexity while maintaining versatility
Solution Approach 2:
The patent merges the processing paths for baseband and modulated signals into a unified architecture. Instead of having separate CDR circuits for each transmission scheme, the design combines them into one shared CDR circuit that receives input from either path via the selector, reducing the total circuit size while supporting multiple transmission schemes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach successfully minimizes the receiver's circuit size and semiconductor chip size, resulting in reduced manufacturing costs while supporting multiple transmission schemes.
Implementation Method 1
a first phase-locked loop (PLL) circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal
Implementation Method 2
a first clock data recovery (CDR) circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock
Data Source
AI summary
A receiver for receiving signals in a plurality of transmission schemes, reducing the circuit size thereof successfully. The receiver for receiving a baseband signal and a modulated signal, includes a first PLL circuit configured to generate a first internal clock based on an external clock synchronized with the baseband signal; a demodulator configured to demodulate the modulated signal to output the demodulated signal; a selector configured to select one of the baseband signal or the demodulated signal; and a first CDR circuit configured to generate a recovered clock and recovered data from the signal selected by the selector, by using the first internal clock.