Memory Package Addressing With Shared CE Lines and CER Selection
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Solution Overview
Problem
The increasing demand for higher-capacity storage devices, such as solid state drives, leads to an increase in the number of chip enable (CE) pins and CE signal lines, which in turn increases the size and manufacturing costs of the controller.
Innovation Solution
A storage device design that reduces the number of CE pins and CE signal lines by using a common CE signal line and command signal line for multiple packages, with package and die identification bits to selectively address individual dies within the packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more memory packages are mounted to increase storage capacity, then the capacity of the storage device is improved, but the number of CE pins and CE signal lines increases
Solution Approach 1:
Multiple memory packages share a common CE signal line, merging what would traditionally be separate signal lines into a single shared line. This is achieved by using package identification bits to distinguish between different memory packages on the same signal line, allowing one signal line to serve multiple packages without signal conflicts.
Solution Approach 2:
The common CE signal line serves multiple memory packages simultaneously by incorporating package identification bits that enable the signal line to universally address different packages. This multi-functional approach allows a single signal line to perform the function of multiple dedicated signal lines would provide.
2Quantity of substance
If more memory packages are mounted to increase storage capacity, then the capacity of the storage device is improved, but the size of the controller increases
Solution Approach 1:
Multiple CE signal lines are merged into a single common CE signal line, reducing the physical number of signal lines that must be routed to and from the controller. This merging directly reduces the controller's pin count and the space required for signal line routing, thereby reducing overall controller size.
Solution Approach 2:
Instead of providing separate dedicated CE signal lines for each memory package, the system uses a single shared signal line with identification bits that copy the addressing function across multiple packages. This reduces the physical infrastructure while maintaining the ability to control multiple packages.
3Quantity of substance
If more memory packages are mounted to increase storage capacity, then the capacity of the storage device is improved, but the manufacturing costs increase
Solution Approach 1:
By merging multiple CE signal lines into one common signal line, the system reduces the total number of components that must be manufactured, assembled, and tested. This reduction in component count directly lowers manufacturing costs while still supporting multiple memory packages through the package identification bit mechanism.
Data Source
AI summary
Disclosed is a storage device including a first package including first dies, a second package including second dies, a first chip enable (CE) signal line connected in common to the first and second packages, a first command signal line connected in common to the first and second packages, and a controller configured to select one die of dies included in packages connected in common to the first CE signal line by applying a CE signal to the first CE signal line and a chip enable reduction (CER) command signal to the first command signal line. The CER command signal includes at least one package identification bit for package selection and at least one die identification bit for die selection, and each of the first and second packages includes at least one identification pin applied with at least one package identification voltage respectively corresponding to at least one package identification bit.