Shared-Channel FinFET Pixel Transistors for Random Noise Reduction
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Solution Overview
Problem
Existing imaging elements face challenges in reducing random noise from amplification and selection transistors, leading to deteriorated image quality due to the limitations of conventional methods in minimizing pixel noise.
Innovation Solution
The use of multigate transistors, specifically FinFETs, for both selection and amplification transistors in the imaging element, which allows for longer effective channel widths and reduced distance between gate electrodes, thereby minimizing random noise and pixel unit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistors are used for selection and amplification, then the structure is simpler, but random noise increases and image quality deteriorates
Solution Approach 1:
The patent transitions from planar transistors to FinFET (three-dimensional) transistors. The FinFET structure provides a vertical channel with gate electrodes wrapping around the channel from multiple sides, creating a three-dimensional configuration that increases the effective channel width and improves control over random noise while maintaining compact footprint.
Solution Approach 2:
The patent implements nested gate electrodes where a first gate electrode and a second gate electrode are positioned at different vertical levels, with the second gate electrode partially overlapping the first. This nested arrangement allows both selection and amplification functions within a compact vertical space, reducing pixel unit size while maintaining transistor performance.
2Object-generated harmful factors
If vertical channel is formed in amplification transistor, then afterimage and dark current are reduced, but random noise from transistors remains difficult to reduce
Solution Approach 1:
The patent employs FinFET structures for both selection and amplification transistors, creating vertical channels that provide multi-directional gate control. This three-dimensional configuration increases the effective channel width and enhances control over carrier flow, simultaneously addressing afterimage/dark current reduction and random noise suppression that cannot be achieved with conventional planar structures.
Solution Approach 2:
The patent combines multiple gate electrodes (first gate electrode and second gate electrode) in a nested arrangement to form a multi-gate transistor structure. This merged configuration integrates selection and amplification functions with enhanced control capability, allowing simultaneous optimization of afterimage reduction and random noise suppression through coordinated gate control.
3Reliability
If multigate transistors are used, then random noise is reduced and image quality improves, but manufacturing complexity increases
Solution Approach 1:
The patent implements a nested gate electrode structure where the second gate electrode is positioned to partially overlap the first gate electrode in the vertical direction. This nested configuration allows both gates to be formed using sequential deposition and patterning processes, enabling multigate functionality while maintaining compatibility with existing CMOS manufacturing workflows.
Solution Approach 2:
The FinFET structure utilizes vertical dimensionality to achieve multi-gate control without significantly increasing lateral footprint. The vertical channel and wrapped gate electrodes can be formed using established etching and deposition techniques, making the three-dimensional structure manufacturable with minimal increase in process complexity.
4Area of stationary object
If gate electrodes are positioned closer together, then pixel unit size is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The nested gate electrode configuration allows the second gate electrode to be positioned in partial overlap with the first gate electrode in the vertical direction. This nesting reduces the lateral distance between functional gates while the vertical separation maintains manufacturing tolerability, achieving compact pixel units without excessive precision requirements.
Solution Approach 2:
By utilizing the vertical dimension for gate electrode placement, the patent reduces lateral spacing requirements. The FinFET structure's vertical channel allows gates to be stacked at different heights, compacting the pixel unit footprint while maintaining manufacturable dimensional tolerances through three-dimensional positioning.
Data Source
AI summary
An imaging element and device configured for reduced image quality deterioration are disclosed. In one example, a pixel unit of the imaging element includes a selection transistor and an amplification transistor each constituted by a multigate transistor. The selection transistor and amplification transistor may be a FinFET that includes a silicon channel having a fin shape. Moreover, gates of the selection transistor and the amplification transistor may be formed on an identical silicon channel having a fin shape. Furthermore, for example, an ion having a smaller thermal diffusivity than a thermal diffusivity of boron or phosphorous is injected into the silicon channel of the selection transistor. In addition, for example, a work function of a material of a gate electrode of the selection transistor is different from a work function of a material of a gate electrode of the amplification transistor.