Shared-Channel Memory Clock Phasing for Lower Power DRAM
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Solution Overview
Problem
The performance of Dynamic Random Access Memory (DRAM) needs improvement to meet increasing user requirements across various application fields, particularly in terms of reducing the number of communication channels, cost, and power consumption.
Innovation Solution
A memory system where multiple storage chips share a common communication channel with a control chip, utilizing different clock signals for different sets of storage chips to facilitate information interaction, thereby reducing the number of required communication channels and improving storage density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple storage chips use separate communication channels with the control chip, then communication reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
Multiple storage chips share a common communication channel with the control chip, merging multiple separate communication paths into a single shared channel. This reduces the total number of communication channels required while maintaining reliable data transmission through time-multiplexed access controlled by phase-differentiated clock signals.
Solution Approach 2:
The common communication channel serves multiple storage chips simultaneously, making the channel universal rather than dedicated to a single chip. The channel can transmit data to or from any of the connected storage chips by selecting the appropriate chip based on clock phase timing, reducing overall system complexity.
2Device complexity
If multiple storage chips share a common communication channel, then device complexity and manufacturing cost are reduced, but data transmission speed may be limited by channel contention
Solution Approach 1:
Different sets of storage chips operate on different clock phases, creating periodic transmission windows for each set. This time-multiplexed approach allows multiple chips to share the common channel without simultaneous contention, as each chip set transmits during its designated phase window, maintaining high data transmission speed.
Solution Approach 2:
The system dynamically assigns different clock phases to different storage chip sets, allowing flexible time-division multiplexing of the common communication channel. This dynamic phase assignment enables the system to optimize data transmission by alternating active transmission between different chip sets during different clock cycles.
3Speed
If separate communication channels are used for each storage chip, then data transmission speed is improved, but power consumption and manufacturing cost increase
Solution Approach 1:
Multiple communication channels are merged into a single common channel that serves all storage chips. By sharing the channel infrastructure, the system reduces the total power consumption associated with maintaining multiple separate channel circuits while achieving comparable effective data transmission speed through time-multiplexed access.
4Productivity
If more communication channels are provided for multiple storage chips, then storage performance is improved, but manufacturing cost and device area increase
Solution Approach 1:
Storage chips are segmented into different sets that operate on different clock phases. This segmentation allows the system to achieve high storage performance by enabling parallel operations across different phase groups while sharing the common communication channel, thereby reducing manufacturing cost compared to providing dedicated channels for every chip.
Data Source
AI summary
A memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips include a first storage chip set and a second storage chip set, the storage chips in the first storage chip set are configured to perform information interaction with the control chip by adopting a first clock signal, the storage chips in the second storage chip set are configured to perform information interaction with the control chip by adopting a second clock signal, and phase of the first clock signal is different from phase of the second clock signal.