Shared-Channel Memory With Phase-Shifted Clocks for Lower Power
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Solution Overview
Problem
Existing Dynamic Random Access Memories (DRAMs) face issues of high power consumption and cost due to the need for multiple communication channels with each storage chip, leading to inefficiencies in data transmission and storage performance.
Innovation Solution
Implementing a memory structure where multiple storage chips share a communication channel, with different clock phases for separate chip sets, allowing simultaneous data transmission and reducing the number of required communication channels, thereby decreasing power consumption and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple storage chips are connected to control chips via separate communication channels, then information interaction reliability is improved, but power consumption and cost increase
Solution Approach 1:
Multiple storage chips share a common communication channel with the control chip, merging separate communication paths into a single shared channel. This reduces the total number of communication channels required, thereby lowering power consumption and cost while maintaining reliable information interaction through time-multiplexed access controlled by phase-differentiated clock signals.
Solution Approach 2:
The common communication channel serves multiple storage chips simultaneously, making the channel universal rather than dedicated to a single chip. The channel can be dynamically allocated to different storage chips based on their operational needs, improving resource utilization and reducing overall system power consumption.
2Reliability
If multiple storage chips are connected to control chips via separate communication channels, then information interaction reliability is improved, but manufacturing cost increases
Solution Approach 1:
Multiple storage chips share a common communication channel with the control chip, merging separate communication paths into a single shared channel. This reduces the total number of communication channels required, thereby lowering power consumption and cost while maintaining reliable information interaction through time-multiplexed access controlled by phase-differentiated clock signals.
Solution Approach 2:
The common communication channel serves multiple storage chips simultaneously, making the channel universal rather than dedicated to a single chip. The channel can be dynamically allocated to different storage chips based on their operational needs, improving resource utilization and reducing overall system power consumption.
3Use of energy by moving object
If multiple storage chips share a common communication channel, then power consumption and cost are reduced, but data transmission continuity may be affected
Solution Approach 1:
The system employs periodic clock signals with different phases to control access to the common communication channel. Each storage chip is assigned specific time windows based on phase-differentiated clock signals, creating a periodic, structured access pattern that ensures continuous and orderly data transmission without conflicts or idle periods.
Solution Approach 2:
By using multiple clock signals with different phases, the system ensures that while one storage chip is transmitting data, another can simultaneously access the channel during different phase windows. This overlapping, continuous operation eliminates idle periods and maintains uninterrupted data transmission flow.
Data Source
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AI summary
The embodiment of the present disclosure provides a memory, including: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips include a first storage chip set and a second storage chip set, the storage chips in the first storage chip set are configured to perform information interaction with the control chip by adopting a first clock signal, the storage chips in the second storage chip set are configured to perform information interaction with the control chip by adopting a second clock signal, and phase of the first clock signal is different from phase of the second clock signal.