Shared-Channel Nonvolatile Memory Phase Calibration for High-Speed I/O
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Solution Overview
Problem
Existing nonvolatile memory devices face challenges in high-speed communication due to phase mismatches between clock signals, leading to reduced data window effectiveness and performance deterioration.
Innovation Solution
The implementation of a nonvolatile memory device with a phase calibration mechanism, where a first memory chip generates a signal from a clock signal received from a controller, and a second memory chip generates a second signal, with a phase difference correction operation to align the phases of both signals, utilizing a delay circuit and phase detector to adjust the clock signal and improve data window efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If nonvolatile memory devices operate at high frequency, then communication speed improves, but phase mismatch between clock signals worsens
Solution Approach 1:
The patent performs phase calibration operations before high-speed communication begins. The delay circuit pre-adjusts the second clock signal based on detected phase differences, ensuring signals are synchronized before high-frequency operation starts, thus preventing phase mismatch issues during high-speed communication
Solution Approach 2:
The patent implements a feedback mechanism where the phase detector continuously monitors phase differences between clock signals from different memory chips and provides feedback to the delay circuit. This closed-loop system dynamically adjusts timing to maintain phase alignment during high-speed operation, resolving the contradiction between speed and reliability
2Reliability
If phase calibration is performed to align signals, then data window effectiveness improves, but calibration time increases
Solution Approach 1:
The patent performs phase calibration only when necessary (e.g., when phase mismatch exceeds a threshold or during specific operation modes) rather than continuously. This partial action approach achieves sufficient data window effectiveness without incurring excessive calibration time penalties during normal operation
Solution Approach 2:
The patent dynamically adjusts the calibration frequency and depth based on operating conditions. During high-speed communication where phase stability is critical, more frequent calibration is performed. During lower-speed operations, calibration is reduced or skipped, thus optimizing the balance between data window effectiveness and calibration time
Data Source
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AI summary
Described is a nonvolatile memory. The nonvolatile memory device includes a first memory chip and a second memory chip connected to a controller through the same channel. The first memory chip generates a first signal from a first internal clock signal based on a clock signal received from the controller. The second memory chip generates a second signal from a second internal clock signal based on the clock signal, and performs a phase calibration operation on the second signal on the basis of a phase of the first signal by delaying the second internal clock signal based on a phase difference between the first and second signals.