Shared Charge Pump Duty Cycle Correction for PLL Clock Circuits

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Solution Overview

Problem

Conventional clock generation circuits in semiconductor devices require multiple charge pumps for duty cycle correction, leading to high power consumption and large chip area due to the plurality of charge pumps needed.

Innovation Solution

A clock generation circuit with a shared charge pump that adjusts the voltage level for multiple amplification parts, reducing the number of charge pumps required and thereby minimizing power consumption and chip size.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple charge pumps are used for duty cycle correction in each amplification part, then the duty cycle correction performance is improved, but the power consumption and chip area increase

Engineering Contradiction:

Improveduty cycle correction performanceVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent merges multiple charge pumps into a single shared charge pump that serves multiple amplification parts. The shared charge pump generates a control signal that is distributed to multiple amplification parts, each containing a duty cycle correction circuit. This combining approach maintains duty cycle correction functionality while reducing the total number of charge pumps, thereby lowering power consumption and chip area.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The shared charge pump is designed to perform multiple functions by serving different amplification parts simultaneously. It generates control signals that can be applied to multiple duty cycle correction circuits, making a single component perform the role of what would traditionally require multiple separate charge pumps.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If multiple charge pumps are used for duty cycle correction in each amplification part, then the duty cycle correction performance is improved, but the chip area increases

Engineering Contradiction:

Improveduty cycle correction performanceVSAvoidchip area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

Inventive Principle:

Principle #5Merging (Combining)

3Use of energy by stationary object

If a shared charge pump is used for multiple amplification parts, then power consumption and chip area are reduced, but the control voltage ripple increases

Engineering Contradiction:

Improvepower consumptionVSAvoidcontrol voltage ripple

Core Design Contradiction:

Use of energy by stationary objectVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an intermediary low-pass filter between the shared charge pump and the amplification parts. This filter acts as a mediator that smooths the control signal generated by the charge pump, removing high-frequency ripple components while preserving the DC control voltage needed for duty cycle correction. This intermediary element effectively decouples the ripple generation from the duty cycle control function.

Inventive Principle:

Principle #24Intermediary (Mediator)

4Area of stationary object

If a shared charge pump is used for multiple amplification parts, then chip area is reduced, but the control voltage ripple increases

Engineering Contradiction:

Improvechip areaVSAvoidcontrol voltage ripple

Core Design Contradiction:

Area of stationary objectVSObject-generated harmful factors

Solution Approach 1:

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS7567106B2Duty cycle correction circuit, clock generation circuits, semiconductor devices using the same, and method for generating clock signal

Publication Date: 2009.07.28 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor device and method of generating clock signals where a phase lock loop (PLL), or a delay lock loop (DLL), comprises a duty cycle correction circuit (DCC) having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate internal clock signals. The shared charge pump adjusts voltage level of control signal (VC) in response to the internal clock signals and provides the control signal VC to each of the amplification parts.