Shared Charge Pump for Concurrent Flash Memory Operations
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Solution Overview
Problem
The large footprint of charge pumps in semiconductor integrated circuits occupied about 20% of the IC area, limiting the efficiency and space for embedded flash memory in devices.
Innovation Solution
The implementation of a shared charge pump and address storage device across two circuits within an integrated circuit, allowing concurrent operations and reducing the number of input pins, thereby minimizing the chip area and simplifying design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a charge pump is included in each flash memory circuit, then high voltage generation capability is ensured, but the chip area increases significantly (occupying about 20% of IC area)
Solution Approach 1:
The patent merges the charge pump functionality across multiple flash memory circuits by sharing a common charge pump circuit between two circuits. This allows both circuits to access flash memory cells requiring high voltage for erase or program operations without each circuit having its own dedicated charge pump, thereby reducing the overall chip area occupied by charge pump circuits.
Solution Approach 2:
The shared charge pump circuit serves multiple functions by providing high voltage generation capability to both Circuit A and Circuit B simultaneously. This universal charge pump can support erase operations, program operations, and read operations across different flash memory cells in both circuits, eliminating the need for separate charge pumps in each circuit.
2Adaptability or versatility
If separate charge pumps are provided for each circuit, then independent high voltage generation is achieved, but the number of input pins and device complexity increases
Solution Approach 1:
The patent combines the high voltage generation resources by providing a shared charge pump circuit that serves both circuits. This reduces the total number of input pins required, as both circuits can share the same control signals and power supply connections for the common charge pump, thereby simplifying the overall device architecture.
Solution Approach 2:
The shared charge pump circuit is designed to universally serve both Circuit A and Circuit B, providing high voltage generation capability on demand. The circuit includes control logic that can selectively activate the charge pump for different operations (erase, program, read) in either circuit, maintaining adaptability while reducing complexity.
3Reliability
If charge pump occupies large area in IC, then high voltage generation is ensured, but the footprint of IC increases, limiting embedded flash memory usage
Solution Approach 1:
The patent merges the charge pump functionality across multiple flash memory circuits by sharing a common charge pump circuit between two circuits. This allows both circuits to access flash memory cells requiring high voltage for erase or program operations without each circuit having its own dedicated charge pump, thereby reducing the overall chip area occupied by charge pump circuits and increasing the available area for embedded flash memory.
Solution Approach 2:
The shared charge pump circuit serves multiple functions by providing high voltage generation capability to both circuits simultaneously. This universal charge pump can support erase operations, program operations, and read operations across different flash memory cells in both circuits, eliminating the need for separate charge pumps in each circuit and maximizing flash memory utilization.
Data Source
AI summary
A device comprises an address storage device. A first circuit includes a first flash memory, configured to sequentially receive first and second addresses and store the first address in the address storage device. The first circuit has a first set of control inputs for causing the first circuit to perform a first operation from the group consisting of read, program and erase on a cell of the first flash memory corresponding to a selected one of the first and second addresses. A second circuit includes a second flash memory, configured to receive the second address. The second circuit has a second set of control inputs for causing the second circuit to read data from a cell of the second flash memory corresponding to the second address while the first operation is being performed.