Shared Checksum Circuit for Multi-Block CRC Calculation

The patent combines multiple checksum calculation circuits into a single shared circuit. The same CRC calculation circuit is used to compute checksums for different data blocks (data block 1 with end-to-end checksum, data block 2 with link checksum) by resetting the circuit between calculations. This merging approach maintains the ability to detect errors in multiple layers while significantly reducing the overall circuit complexity compared to having separate dedicated circuits for each checksum.

The CRC calculation circuit is designed as a universal multi-functional unit that can calculate different types of checksums (end-to-end checksum, link checksum) for multiple data blocks. The circuit achieves multi-functionality through reset mechanisms and configurable input data, allowing one circuit to perform the work of what would traditionally require multiple separate circuits, thereby reducing device complexity while maintaining comprehensive error detection capability.

The patent merges multiple checksum calculation operations into a single shared circuit that processes data blocks sequentially. Instead of having multiple independent circuits operating in parallel (which would maintain accuracy but increase complexity), the shared circuit processes each data block in sequence with reset operations, achieving a balance between accuracy maintenance and improved processing efficiency through resource sharing.

The circuit performs preliminary reset operations between checksum calculations to ensure accuracy is maintained. By clearing the accumulator and shift register before each new checksum calculation, the circuit guarantees calculation accuracy while using the same hardware resources for multiple calculations, thereby improving overall processing speed compared to having multiple dedicated circuits.

The CRC calculation circuit is designed as a universal unit that can handle multiple data block lengths (e.g., 512 bytes, 1024 bytes, 2048 bytes) without requiring separate dedicated circuits for each length. The circuit achieves this versatility through configurable input data loading and reset mechanisms, allowing the same hardware to adapt to different block sizes by simply reloading the appropriate data and resetting the accumulation registers, thereby avoiding the complexity increase that would result from having separate circuits for each block length.

The circuit supports multiple data block lengths by changing operational parameters (data input size, reset timing, accumulation count) rather than changing the physical circuit structure. The same CRC polynomial and calculation logic are used, but the circuit adapts to different block lengths by adjusting how data is loaded and processed, maintaining circuit simplicity while achieving high adaptability to various data block sizes.