Shared Clock Monitoring for Area-Efficient Fault Detection
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Solution Overview
Problem
Conventional integrated circuits require multiple clock monitoring units (CMUs) to monitor multiple clock signals, which occupy significant surface area and are inefficient in terms of space utilization.
Innovation Solution
A single clock monitoring unit (CMU) with a toggle signal generator and distributed clock signal detectors is used to detect faults in multiple clock signals across an integrated circuit, allowing for efficient monitoring with reduced surface area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clock monitoring units (CMUs) are implemented to monitor multiple clock signals, then the reliability of clock signal monitoring is improved, but the surface area occupied by the CMUs increases significantly
Solution Approach 1:
The patent merges the functionality of multiple separate CMUs into a single shared CMU that can monitor multiple clock signals. The shared CMU uses a single toggle signal generator and multiple clock signal detectors that are distributed throughout the integrated circuit, eliminating the need for multiple dedicated CMUs and significantly reducing the surface area occupied by monitoring circuitry.
Solution Approach 2:
The single CMU is designed with universal functionality to monitor multiple different clock signals across various logic circuits. The toggle signal generator creates a reference signal that can be compared against multiple clock signals, and the distributed detectors can identify any clock signal, making the single CMU capable of performing the work of multiple dedicated monitoring units.
2Reliability
If multiple clock monitoring units (CMUs) are implemented to monitor multiple clock signals, then the detection capability for clock faults is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple monitoring functions into a single integrated CMU structure. Instead of having separate CMUs for different clock signals, the design merges the toggle signal generation and multiple detection functions into one unit, reducing the overall complexity of the monitoring system while maintaining comprehensive fault detection capability.
Solution Approach 2:
The monitoring system is segmented into distributed clock signal detectors that are placed at various locations throughout the integrated circuit where clock signals are needed. These distributed detectors work in conjunction with the single shared CMU, allowing complex monitoring of multiple signals without requiring a single complex monolithic unit.
Data Source
AI summary
A system and method for detecting a loss of clock signal condition is presented. In various embodiments, a reference clock signal by a clock monitoring system. A toggle signal is generated using the reference clock signal and a clock detector output signal is generated. The clock detector output signal is equal to the toggle signal when a monitored clock signal is received. The clock detector output signal to the toggle signal and, when the clock detector output signal is not equal to toggle signal, an output signal indicative of a loss of clock signal condition is generated. In various embodiments, the clock monitoring system is utilized in conjunction with various systems, including automotive controllers, and the like.