Shared-Clock Flip-Flop Circuit for Lower Area and Power
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Solution Overview
Problem
Sequential cells or flip-flops occupy a substantial portion of digital design area and consume significant power in digital circuits, necessitating a reduction in area and power consumption.
Innovation Solution
The implementation of a flip-flop circuit that shares clock transistors among its components, including a clock inverter, tri-state inverter, master latch, slave latch, and output inverter, to reduce the overall area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If traditional flip-flop circuit design is used, then functional completeness is maintained, but area consumption increases (occupying 30%-40% of digital design area)
Solution Approach 1:
The patent merges the clock inverter functionality into the tri-state inverter by sharing the second PMOS transistor and second NMOS transistor between both circuits. This consolidation eliminates redundant clock transistors and reduces the overall flip-flop area while maintaining complete functionality.
Solution Approach 2:
The second PMOS transistor and second NMOS transistor serve dual purposes: they function as clock transistors for the tri-state inverter and simultaneously as clock transistors for the clock inverter. This multi-functionality reduces the total transistor count and minimizes area consumption.
2Use of energy by stationary object
If traditional flip-flop circuit design is used, then functional completeness is maintained, but power consumption increases (accounting for about 20% of digital power)
Solution Approach 1:
By merging the clock inverter and tri-state inverter into a single integrated structure with shared clock transistors, the patent reduces the total number of active devices. Fewer transistors mean lower dynamic power consumption while maintaining the necessary functionality for clock signal generation and data transmission.
Solution Approach 2:
The shared second PMOS and second NMOS transistors perform multiple functions simultaneously, reducing redundant switching activity. This multi-functionality decreases the overall power consumption by eliminating duplicate clock signal distribution paths.
Data Source
AI summary
A flip-flop having first and second shared transistors. The flip-flop including a tri-state inverter and a master latch configured to receive an output of the tri-state inverter. The flip-flop also having a slave latch coupled to the master latch, the slave latch including a slave tri-state inverter. The flip-flop further having an output inverter coupled to receive one of an output of the slave latch and an output of the master latch and configured to generate a flip-flop output. The first shared transistor configured to receive a clock signal and having a drain terminal coupled a first transistor in the tri-state inverter and a second transistor in the slave tri-state inverter. The second shared transistor configured to receive an inverted clock signal and having a drain terminal coupled a third transistor in the tri-state inverter and a fourth transistor in the slave tri-state inverter.