Shared-Clock Dual-Edge Flip-Flop for Lower Clock Power
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Solution Overview
Problem
Modern electronic devices face challenges in achieving low power consumption and high performance at ultra-low temperatures and voltages, as reducing supply voltage can lead to performance loss and increased leakage power, while ultra-low-temperature operation requires extreme low voltage to manage cooling costs effectively.
Innovation Solution
A shared clock dual edge-triggered multiplexer D scan flip-flop circuit is designed with a reduced number of clock transistors, allowing for efficient operation at half frequency, which reduces clock power dissipation and maintains performance by sharing clock transistors among circuit elements, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If supply voltage is lowered to reduce power consumption, then power efficiency is improved, but performance deteriorates due to degradation of transistor ION current
Solution Approach 1:
The patent employs ultra-low-temperature operation to fundamentally change the operating parameters of the circuit. This temperature parameter change enables the circuit to achieve both low power consumption and high performance by exploiting the improved transistor characteristics at cryogenic temperatures, where mobility increases and sub-threshold slope steepens, allowing efficient operation at extreme low voltages
2Productivity
If low-Vt transistor is used to recuperate ION current reduction, then ION current is improved, but leakage power significantly increases
Solution Approach 1:
The patent changes the temperature parameter to ultra-low temperatures, which fundamentally alters the transistor behavior. At these temperatures, the natural transistor characteristics provide high ION current without the need for low-Vt devices, thereby avoiding the leakage power penalty while maintaining or improving performance
3Productivity
If ULT operation is implemented to increase mobility and ION/IOFF ratio, then transistor performance is improved, but extreme low voltage operation is required to manage cooling costs
Solution Approach 1:
The patent implements ultra-low-temperature operation as a fundamental parameter change that simultaneously achieves high transistor performance and enables efficient low-voltage operation. The cryogenic temperature environment naturally provides enhanced mobility and steeper sub-threshold slopes, allowing the circuit to operate at extreme low voltages which reduces dynamic power consumption and offsets the cooling requirements
4Loss of energy
If clock frequency is halved to reduce clock power, then clock power dissipation is reduced by approximately 50%, but performance may be compromised
Solution Approach 1:
The patent changes the temperature parameter to ultra-low temperatures, which enables the circuit to maintain high performance even at half frequency operation. The improved transistor characteristics at cryogenic temperatures compensate for the reduced clock frequency, allowing the system to achieve both lower clock power dissipation and sustained performance
Solution Approach 2:
The patent employs dual edge-triggered flip-flops that utilize both rising and falling edges of the clock signal. This periodic action at both edges allows the circuit to effectively double the data capture rate, compensating for the halved clock frequency and maintaining overall system performance while reducing clock power consumption
Data Source
AI summary
Some embodiments include an apparatus having a flip-flop circuit, which can include a first tristate inverter, a second tristate inverter including an input node coupled to an input node of the first tristate inverter; a first additional inverter including, and a second additional inverter including an output node coupled to an output node of the first additional inverter; a first memory including a first memory node coupled to an output node of the second tristate inverter, and a first additional memory node coupled to an input node of the first additional inverter; and a second memory including a second memory node coupled to an output node of the first tristate inverter, and a second additional memory node coupled to an input node of the second additional inverter.