Shared Clock Source Frequency Error Correction for Dual Modems
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Solution Overview
Problem
Current mobile communication terminals with Dual-SIM-Dual-Call (DSDC) feature, which use two modems with a shared clock source, face challenges in quickly correcting frequency errors, leading to potential call failures and performance issues due to long response times.
Innovation Solution
A method and apparatus for adjusting frequency errors in mobile communication terminals with multiple modems using a shared clock source, involving steps to obtain and synthesize adjusted clock source values based on frequency errors and thresholds, balancing modem performance by adjusting the clock source frequency to correct errors quickly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If two modem systems use a same clock source to reduce cost, then device complexity and cost are reduced, but frequency error correction response time increases leading to call failures
Solution Approach 1:
The patent segments the frequency error correction process into two independent paths: a fast correction path that directly adjusts the clock source frequency based on synthesized adjusted values from multiple modems, and a traditional slow correction path that uses PLL (Phase Locked Loop) for precise but time-consuming correction. This segmentation allows the system to achieve rapid initial correction without requiring separate clock sources for each modem, thus resolving the contradiction between cost/complexity and response time.
Solution Approach 2:
The patent performs preliminary frequency error estimation and clock source adjusted value synthesis before actual frequency correction occurs. By pre-calculating the adjusted values from multiple modems and synthesizing them into a comprehensive correction value, the system prepares the correction data in advance, enabling rapid response when frequency error detection occurs without the delays associated with traditional PLL-based correction methods.
2Loss of time
If two modem systems use different clock sources to enable independent frequency correction, then frequency error correction speed is improved, but device complexity and cost increase
Solution Approach 1:
The patent merges the frequency error correction capabilities of multiple modems by synthesizing their individual adjusted values into a single comprehensive adjusted value for the shared clock source. This merging approach allows the system to leverage the correction needs of all modems while maintaining a single clock source, achieving fast correction response without duplicating clock source hardware, thus resolving the contradiction between correction speed and system complexity.
Solution Approach 2:
The patent introduces a clock source management module as an intermediary that receives frequency error information from multiple modems, synthesizes their adjusted values, and controls the shared clock source. This intermediary component enables coordinated frequency error correction across all modems using a single clock source, achieving fast correction response without requiring independent clock sources for each modem, thus resolving the contradiction between correction speed and system complexity.
3Device complexity
If PLL correction is used for frequency error correction in shared clock source systems, then cost is reduced, but correction accuracy and reliability decrease due to long response time
Solution Approach 1:
The patent implements a dynamic frequency error correction mechanism that adapts the correction speed and method based on system conditions. The system dynamically synthesizes adjusted values from multiple modems and applies rapid clock source frequency adjustment when frequency errors are detected, rather than relying solely on the static, slow PLL correction process. This dynamic approach maintains the simple shared clock source configuration while significantly improving correction speed and call connection reliability.
Data Source
AI summary
Handling a frequency error (FEQ) of a terminal which includes a plurality of modems using a same clock source includes: obtaining the FEQ, which is a difference between a carrier frequency of a received signal and a nominal frequency for each modem; obtaining a FEQ threshold of the received signal in a current service based on the FEQ; obtaining an adjusted value of the clock source corresponding to each modem based on the FEQ and the FEQ threshold; obtaining a synthesized adjusted value of the clock source based on the adjusted values of all the modems; and adjusting the frequency of the clock source based on the synthesized adjusted value of the clock source. The FEQ of the mobile communication terminal can be quickly corrected by adjusting the clock source's frequency, and, by considering the FEQ of all the modems, the modems' performances may be balanced.