Shared Clock Control Using Hardware Voting in Multi-SoC Sleep States
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Solution Overview
Problem
In traditional computing systems with multiple SoCs, turning on an external shared clock requires waking up the processor of the first SoC, leading to unnecessary power consumption and reduced battery life.
Innovation Solution
Implementing a clock control system with input pins that allow second SoCs to directly communicate with the first SoC's clock control system, enabling them to turn the external shared clock on or off without waking up the processor, using a hardware-based voting system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor of the first SoC is used to control the external shared clock, then the clock can be turned on when needed, but the processor must be woken up which increases power consumption
Solution Approach 1:
A dedicated clock control system is introduced as an intermediary component between the SoCs and the external shared clock. This control system includes input pins that directly receive clock enable signals from second SoCs without requiring processor intervention. The control system autonomously manages clock activation based on these signals, eliminating the need to wake up the processor and thus reducing power consumption while maintaining reliable clock control.
2Duration of action of moving object
If the processor is kept in low power mode, then battery life is extended, but second SoCs cannot request clock activation without waking the processor
Solution Approach 1:
The clock control system is designed to serve itself by directly receiving clock enable signals from second SoCs through dedicated input pins. This self-service mechanism allows second SoCs to autonomously request and activate the external shared clock without involving the processor. The control system independently processes these requests and manages clock state transitions, enabling battery-powered processors to remain in low power mode while maintaining full clock request capability across all SoCs.
3Loss of time
If direct communication paths are added from second SoCs to the clock control system, then response time is reduced, but device complexity increases
Solution Approach 1:
The clock control system is segmented into distinct functional components: dedicated input pins for receiving clock enable signals, control logic for processing these signals, and output mechanisms for clock activation. This segmentation allows direct communication paths from second SoCs to the control system, enabling rapid clock activation. The modular structure manages complexity by separating signal reception, processing, and execution functions, making the system easier to design and maintain despite the added direct communication paths.
Data Source
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AI summary
The present disclosure provides computer-implemented methods, systems, and devices for controlling an external shared clock in a computing system with a plurality of system on a chips (SoCs). To do so, while a first SoC is in a low power mode, the second SoC receives a wake-up input that causes the second SoC to exit a low power mode. The second SoC asserts a clock request signal line to activate an external shared clock. The clock control system determines a state associated with the external shared clock, wherein the external shared clock is external to the first SoC. The clock control system, in accordance with a determination that the external shared clock is in an off state, transmits a signal to the external shared clock to cause the external shared clock to enter a startup state and begin producing a shared clock signal.