Shared Clock Recovery Circuit for Multi-Lane Jitter Tolerance
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Solution Overview
Problem
Current clock recovery systems in digital data communication protocols face limitations in jitter tolerance due to variations in data clock frequencies and power supply noise, which narrow the data eye and restrict maximum data rates.
Innovation Solution
A global clock recovery circuit is implemented that uses shared frequency and phase tracking loops, along with voltage- or current-controlled delay lines, to produce a global recovered clock for multiple lanes, compensating for correlated frequency offsets and jitter, and is integrated with local clock recovery circuits to minimize dither jitter and improve high-frequency jitter tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a local reference clock is used for clock recovery in each lane, then the sampling timing can be adjusted for each lane, but correlated frequency offsets and jitter across lanes cannot be compensated, resulting in narrowed data eye and reduced jitter tolerance
Solution Approach 1:
The patent merges multiple independent local clock recovery circuits into a single shared global clock recovery circuit that serves multiple lanes. This consolidation allows the system to track and compensate for correlated frequency offsets and jitter that affect multiple lanes simultaneously, thereby improving jitter tolerance while maintaining sampling timing accuracy through the shared recovery mechanism.
Solution Approach 2:
The global clock recovery circuit is designed to serve multiple lanes universally, replacing individual lane-specific recovery circuits. This multi-functional approach enables a single circuit to handle clock recovery for all lanes while incorporating mechanisms to track and compensate for correlated disturbances, thus improving overall system reliability without sacrificing measurement precision.
2Adaptability or versatility
If independent clock recovery circuits are used for each lane, then lane-specific timing adjustments are possible, but the system complexity increases and correlated jitter cannot be tracked, limiting maximum data rate
Solution Approach 1:
The patent combines multiple independent clock recovery circuits into a single shared global circuit, reducing device complexity by eliminating redundant components. This merged circuit maintains the ability to provide lane-specific timing adjustments through its output to multiple lanes while adding the capability to track and compensate for correlated jitter, thus improving maximum data rate without proportionally increasing complexity.
Solution Approach 2:
The global clock recovery circuit is designed as a universal solution that serves multiple lanes simultaneously. It provides lane-specific timing adjustments through its distributed outputs while incorporating centralized mechanisms for tracking and compensating correlated disturbances, achieving multi-functionality that reduces overall system complexity compared to independent per-lane circuits.
3Ease of manufacture
If traditional CDR circuits are used without shared frequency tracking, then implementation is simpler, but frequency offsets between lanes cannot be compensated, reducing productivity at high data rates
Solution Approach 1:
The patent implements a shared frequency tracking mechanism that combines the frequency tracking functionality across multiple lanes into a single circuit. This approach maintains relative implementation simplicity compared to fully independent circuits while adding the capability to compensate for frequency offsets, thereby enabling higher productivity at maximum data rates without excessive complexity increase.
Solution Approach 2:
The shared frequency tracking circuit serves as a universal solution for all lanes, providing frequency offset compensation across the entire system. This multi-functional circuit maintains ease of manufacture through its unified design while significantly improving productivity by enabling accurate frequency tracking and compensation that supports high-speed data transmission.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances jitter tolerance, reduces dither jitter, and allows for higher data rates by accurately synchronizing sampling times across multiple lanes, improving the overall performance of clock recovery systems in multi-lane data communication systems.
Implementation Method 1
voltage- or current-controlled delay lines
Implementation Method 2
voltage- or current-controlled delay lines
Implementation Method 3
Phase differences between the recovered clock and the data signals can be detected and used as feedback in the generation of the recovered clock
Data Source
AI summary
This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current-controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.