Shared Clock Circuit Timing Mode Switching for Peripheral Locking
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Solution Overview
Problem
In electronic systems where multiple peripherals share a single clock signal, there is no mechanism to selectively control the clock timing mode, leading to undesired operations when peripherals are not actively communicating with the microprocessor, and the inability to change the clock mode when a peripheral is active.
Innovation Solution
A circuit arrangement where a slave circuit receives an external clock signal from a microprocessor and generates locking signals to manage clock timing modes for peripherals, allowing the microprocessor to send the clock signal in different timing modes based on the operating mode of the peripherals, including a continuous mode for non-volatile memory access and a pulse-slot mode for serial interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal is generated continuously for a particular peripheral, then the peripheral can operate without interruption, but other peripherals may execute undesired operations or enter indefinite states when they are not actively communicating
Solution Approach 1:
The patent segments the clock signal distribution by creating separate clock control paths for different peripherals. The master circuit can independently control the clock signal routing to each peripheral based on their active states, preventing clocked peripherals from executing undesired operations when not in use while maintaining reliable operation when active.
Solution Approach 2:
The patent implements dynamic clock signal control where the master circuit adjusts the clock signal generation mode (continuous or pulsed) based on the real-time operational state of each peripheral. This dynamic adaptation allows the system to switch between continuous clocking for active peripherals and pulsed/ inhibited clocking for inactive ones, eliminating harmful unintended operations.
2Reliability
If the clock signal is generated continuously at constant nominal frequency, then all peripherals can operate at their required rates, but the data exchange rate must be based on the slowest peripheral reducing overall system efficiency
Solution Approach 1:
The patent applies local quality by allowing each peripheral to receive clock signals at its specific required frequency and timing characteristics. The master circuit configures individual clock paths with appropriate frequencies for each peripheral's operational needs, rather than forcing all peripherals to operate at a uniform slowest rate, thereby maintaining timing reliability while maximizing overall data exchange efficiency.
Solution Approach 2:
The patent changes the clock signal parameters (frequency, continuity, pulse duration) dynamically based on which peripheral is actively communicating. When a fast peripheral needs communication, the master circuit generates continuous clock signals at the appropriate high frequency for that specific peripheral, while inhibiting or using pulsed mode for other inactive peripherals, thus optimizing data exchange rates without compromising timing reliability.
3Device complexity
If no chip-select mechanism is implemented, then the device complexity is reduced, but it becomes impossible to selectively control which peripheral receives the clock signal leading to indefinite states
Solution Approach 1:
The master circuit is designed with multi-functionality to perform both data processing and clock signal distribution control. By integrating the clock control functionality within the master circuit that already manages data exchange, the patent achieves peripheral selection and clock management without adding separate chip-select mechanisms, thus maintaining low device complexity while ensuring proper peripheral control and selection.
4Stability of the object's composition
If the microprocessor cannot change the clock generation mode when a peripheral is active, then the system stability is maintained, but the system cannot adapt to different communication requirements of different peripherals
Solution Approach 1:
The patent implements dynamic clock mode switching where the master circuit can change between continuous and pulsed clock generation modes based on which peripheral is actively communicating. The system maintains stability by ensuring smooth transitions and proper state management, while achieving adaptability by selecting the appropriate clock mode (continuous for some peripherals, pulsed for others) according to their specific communication requirements.
Solution Approach 2:
The patent employs periodic or pulsed clock action for certain peripherals instead of continuous clocking. The master circuit can generate clock signals in periodic bursts synchronized with the communication needs of active peripherals, reducing power consumption and preventing unintended operations during inactive periods, while maintaining full adaptability to different peripheral communication patterns.
Data Source
AI summary
In an embodiment, a system includes a slave circuit configured to receive an external clock signal from a master circuit, the slave circuit comprising first and second peripherals configured to receive respective clock signals obtained from the external clock signal, wherein the master circuit is configured to send to the slave circuit the external clock signal according to two different timing modes, wherein the slave circuit comprises a logic circuit configured to provide a locking signal to the first peripheral circuit when the logic circuit detects a given operating mode of the slave circuit, wherein the master circuit is configured to send the external clock signal according to a first timing mode before receipt of the locking signal, and wherein the master circuit is configured, following upon receipt of the locking signal, to send the external clock signal according to a second timing mode different from the first timing mode.