Shared Clock Recovery Circuit for High-Density Memory I/O
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Solution Overview
Problem
Conventional semiconductor memory devices require large area and high power consumption due to the number of clock data recovery (CDR) circuits needed for high-speed signal processing, limiting the number of data transmission channels and increasing power usage.
Innovation Solution
The solution involves grouping signal input/output pads and sharing CDR circuits, with phase detection units and notification units to detect and adjust signal phases, converting parallel signals to serial signals, and adjusting output times based on detected signal transmission states to stabilize high-speed data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If CDR circuits are provided for each data transmission channel to enable high-speed signal processing, then signal transmission reliability is improved, but device area and power consumption increase
Solution Approach 1:
Multiple CDR circuits are merged into a single shared CDR circuit that serves multiple data transmission channels. The phase detection units are configured to sequentially detect phases for different channels, and the delay control unit adjusts delays for multiple channels using one unified delay unit, thereby reducing the total area occupied by CDR circuits while maintaining high-speed signal processing capability across all channels
Solution Approach 2:
The shared CDR circuit is designed to perform multiple functions by sequentially serving different data transmission channels. The phase detection unit can detect phases for various channels in sequence, and the delay control unit can adjust delays for multiple channels, making a single circuit universal for multiple purposes and reducing overall device area
2Reliability
If CDR circuits are provided for each data transmission channel to enable high-speed signal processing, then clock data recovery capability is improved, but power consumption increases
Solution Approach 1:
Multiple CDR circuits are merged into a single shared CDR circuit that sequentially handles clock data recovery for multiple channels. This consolidation reduces the total power consumption because one circuit is shared across multiple channels rather than each channel having its own dedicated circuit, while still maintaining the capability to recover clock data at high speeds for all channels through sequential processing
3Area of stationary object
If the number of CDR circuits is reduced to decrease area and power consumption, then device integration is improved, but signal processing capability may be compromised
Solution Approach 1:
The shared CDR circuit employs dynamic phase detection and delay control mechanisms that can adaptively adjust to different channel requirements. The phase detection unit sequentially detects phases for different channels, and the delay control unit dynamically adjusts delay amounts for each channel based on detected phase differences, enabling the single circuit to maintain high signal processing capability across multiple channels through dynamic adaptation rather than static dedicated circuits
Data Source
AI summary
Circuit and method for recovering clock data in highly integrated semiconductor memory apparatus includes a plurality of signal receiving units configured to receive signals through a plurality of input/output pads and transfer the signals according to a receiving reference clock, the signal receiving units being divided into groups, a plurality of phase detection units configured to detect phases of signals output from the groups of the signal receiving units, a plurality of phase detection control units configured to control the phase detection units so that the phase detection units sequentially detect the phases of the signals output from each of the groups of the signal receiving units and a notification unit configured to output signals output from the phase detection units.