Clock Path Architecture with Shared Phase Sensing for PVT Alignment
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Solution Overview
Problem
High-speed wireline transmitters face challenges in optimizing performance and power consumption, particularly in achieving accurate clock alignment and managing process-voltage-temperature (PVT) variations, which affect jitter and Signal-to-Noise-and-Distortion Ratio (SNDR) due to the complexity of multiplexers and mismatch issues in phase sensor circuits.
Innovation Solution
A clock path architecture with a multiplexer that allows switching between multiple pairs of clock signals, a duty cycle control circuit for optimal duty cycle tracking, and a clock-to-data phase detector for sub-unit interval alignment, reducing power consumption and improving jitter and SNDR performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple phase sensor circuits are used for accurate clock alignment, then clock alignment accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent combines multiple phase sensor circuits into a single integrated phase sensor that can handle multiple clock signals. The phase sensor is shared across multiple clock paths, reducing the overall number of sensors needed while maintaining alignment accuracy through systematic phase comparison and adjustment mechanisms.
Solution Approach 2:
The phase sensor circuit is designed to serve multiple functions by comparing phases across different clock signals from various paths. A single phase sensor can evaluate multiple clock pairs sequentially or in parallel, making the circuit universal rather than dedicated to a single function, thereby reducing overall system complexity.
2Measurement precision
If multiple phase sensor circuits are used for accurate clock alignment, then clock alignment accuracy is improved, but power consumption increases
Solution Approach 1:
Multiple phase sensing functions are merged into a single power-efficient sensor circuit. By sharing the phase sensor across multiple clock paths and using time-multiplexed or systematic comparison approaches, the patent reduces the total power consumption while maintaining the ability to achieve accurate clock alignment across all paths.
Solution Approach 2:
The phase sensor system is designed to automatically adjust and align clock phases without requiring multiple independently powered sensor circuits. The systematic comparison and adjustment mechanism allows the system to self-calibrate, reducing the need for additional power-consuming components.
3Adaptability or versatility
If complex multiplexer circuits are used for clock distribution, then clock signal routing flexibility is improved, but jitter increases
Solution Approach 1:
The clock distribution system is segmented into multiple independent clock paths, each with its own phase adjustment capability. By dividing the system into manageable segments rather than using a single complex multiplexer, the patent reduces jitter accumulation while maintaining routing flexibility through systematic phase alignment of individual segments.
Solution Approach 2:
The system dynamically adjusts phase alignment for each clock path based on real-time measurements. Rather than relying on a static complex multiplexer configuration, the patent uses dynamic phase adjustment mechanisms that adapt to changing conditions, reducing jitter while maintaining flexibility in clock signal distribution.
4Reliability
If systematic phase alignment with adjustment mechanism is implemented, then jitter is reduced, but device complexity increases
Solution Approach 1:
The phase adjustment mechanism uses feedback from the phase sensor to automatically correct clock phase alignment. By implementing a closed-loop feedback system, the patent reduces jitter through systematic adjustment without requiring overly complex manual tuning mechanisms, as the system self-corrects based on measured phase differences.
Solution Approach 2:
The patent replaces complex mechanical or manual adjustment mechanisms with electronic phase adjustment circuits. By using electronic control and digital signal processing techniques, the system achieves precise phase alignment with reduced jitter while keeping the adjustment mechanism complexity manageable through integration and automation.
Data Source
AI summary
A data transmitter with a phase detector, average duty cycle sensor and phase sampler to optimize a clock/data paths. Phase and duty cycle information are provided to a digital control to adjust a timing in the data path and clock path, respectively. The phase detector reads a skew between the data and negative and positive phase clock signals inside a driver. An optimal pulse width delta is determined by the target duty cycle sensor. Using a measured averaged duty cycle sensor, the digital control calculates the duty cycle error to the target value that is needed inside the driver. The phase sampler has a multiplexer which routes the clock signals to phase sensors which determine a phase error based on, e.g., a rising edge-to-rising edge comparison and a falling edge-to-falling edge comparison. In addition, it includes a duty cycle sensor for each clock phase.