Shared Clock Tree PLL Architecture for Low-Noise SoC Timing
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Solution Overview
Problem
Conventional PLL circuits in SoC designs require multiple clock tree circuits, leading to increased power consumption and noise issues due to dedicated power supply signals, which complicates the design and layout of system-on-chip circuits.
Innovation Solution
A PLL architecture that uses a single clock tree circuit to distribute clock signals to multiple sub-systems, incorporating designated PLL circuits with protection circuits for enhanced power supply rejection and realignment circuits to reduce jitter noise, allowing shared global power supply and flexible deployment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple clock tree circuits are used to distribute clock signals to different sub-systems, then each sub-system can receive its required clock signal, but power consumption increases and noise is induced
Solution Approach 1:
The patent merges multiple clock tree circuits into a single shared clock tree circuit that distributes clock signals to multiple sub-systems. The PLL circuit generates a single clock signal that is distributed through this shared clock tree to various sub-systems including CPU, GPU, USB, and SATA circuits, eliminating the need for separate clock trees for each sub-system and thereby reducing power consumption.
Solution Approach 2:
The shared clock tree circuit is designed to serve multiple functions by distributing clock signals to different sub-systems simultaneously. A single clock tree infrastructure supports clock distribution to CPU, GPU, USB, SATA, and other sub-systems, making the clock distribution mechanism universal rather than dedicated to each sub-system.
2Reliability
If multiple dedicated power supply signals are used for sub-PLL circuits, then power supply noise interference is reduced, but device complexity and layout difficulty increase
Solution Approach 1:
The patent introduces a low-dropout (LDO) regulator as an intermediary component between the power supply and the PLL circuit. The LDO regulator filters and conditions the power supply voltage, providing clean power to the PLL while rejecting noise. This intermediary approach maintains power supply noise rejection without requiring multiple dedicated power supply signals.
Solution Approach 2:
The patent changes the power supply parameter from multiple dedicated power supply signals to a single power supply signal combined with an LDO regulator. By adjusting the power supply architecture from multiple independent supplies to one regulated supply, the system achieves similar noise rejection performance with reduced complexity.
3Reliability
If sub-PLL circuits are deployed away from sub-system circuits, then power supply noise interference is avoided, but design layout complexity increases
Solution Approach 1:
The LDO regulator acts as a mediator that enables the PLL circuit to be placed close to sub-system circuits without suffering from power supply noise interference. By providing cleaned and regulated power at the local level, the PLL can be physically proximate to the sub-systems it serves while maintaining noise immunity through the power conditioning provided by the LDO.
Data Source
AI summary
A phase-lock-loop (PLL) circuit includes a reference PLL circuit configured to generate a reference clock signal; a single clock tree circuit, coupled to the reference PLL circuit, and configured to distribute the reference clock signal; and a plurality of designated PLL circuits coupled to the clock tree circuit, wherein the designated PLL circuits are each configured to receive the distributed reference clock signal through the single clock tree circuit and provide a respective clock signal based on the reference clock signal.