Shared Clock Source Wafer-Level Package for Multi-Die Timing

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Solution Overview

Problem

In wafer-level packages with multiple dies, accumulated clock phase drift leads to timing issues and data transfer losses due to process variations, operation condition differences, and power noise, causing setup/hold time violations between clocks in different dies.

Innovation Solution

Implementing an asynchronous first-in first-out (FIFO) buffer in the input circuit of each die, coupled with a flow control scheme, to manage clock phase differences and ensure stable data transfer by buffering data according to the clock source of the other die, thereby concealing accumulated time interval errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If multiple dies each use their own independent clock source, then each die operates independently, but accumulated clock phase drift occurs between dies leading to data transfer loss

Engineering Contradiction:

Improvedata transfer reliabilityVSAvoidclock phase synchronization

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The patent merges the clock source functionality by having one die (the master die) generate a single clock signal that is shared by multiple dies through the interconnect network. This eliminates the accumulation of clock phase drift that would occur if each die had its own independent clock source, as all dies now synchronize to the same clock signal generated by a single clock source.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The interconnect network acts as an intermediary to distribute the clock signal from the master die to all other dies in the package. This mediator approach allows the clock signal to be propagated across dies while maintaining synchronization, preventing the clock phase drift issues that would arise from direct independent clock generation at each die.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If a shared clock source is used across multiple dies, then clock synchronization is improved, but the device complexity increases due to asymmetric clock source configuration

Engineering Contradiction:

Improveclock phase synchronizationVSAvoidclock source configuration

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent segments the clock source functionality by designating one specific die as the master die responsible for clock generation, while other dies are configured as slaves that receive and use the shared clock signal. This segmentation approach simplifies the overall system by clearly defining roles and reducing the complexity of coordinating multiple independent clock sources.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The clock signal generated by the master die serves multiple functions: it provides timing for the master die itself and simultaneously serves as the synchronized clock source for all other dies in the package. This multi-functionality approach reduces device complexity by eliminating the need for separate clock sources while maintaining synchronization across all dies.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS10261928B2Wafer-level package having one die with its clock source shared by multiple dies and associated clock generating method

Publication Date: 2019.04.16 MEDIATEK INC

AI summary

A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.