Shared Clocked Latch Circuit for Lower Flip-Flop Power
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Solution Overview
Problem
Conventional flip-flop circuit architectures in VLSI systems consume significant power due to a large number of clock-activated transistors, leading to high power consumption and voltage drops, especially in highly pipelined microprocessor systems, where reducing clock load and internal node toggling is crucial.
Innovation Solution
The implementation of a shared clock-activated transistor architecture with keeper subcircuits that are clock-gated via shared high or low-supply nodes, reducing the number of clock-activated transistors and maintaining fully-static operation, thereby reducing power consumption and eliminating internal node toggling when the main input signal is constant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flip-flop circuit architectures are used with multiple clock-activated transistors, then reliable data sampling and storage is achieved, but power consumption increases significantly
Solution Approach 1:
The patent merges the clock-activated transistor functionality across multiple latches by sharing a single clock-activated transistor among several latches. This consolidation reduces the total number of clock-activated transistors from multiple per latch to one shared transistor serving multiple latches, thereby significantly reducing power consumption while maintaining reliable data sampling through the shared resource.
Solution Approach 2:
The shared clock-activated transistor performs multiple functions by enabling data sampling for multiple different latches sequentially. This single transistor universally controls the sampling operation across the entire bank of latches, replacing what would traditionally require individual dedicated transistors for each latch, thus reducing overall power consumption.
2Reliability
If multiple clock-activated transistors are used in flip-flop circuits, then data sampling capability is maintained, but voltage drops increase
Solution Approach 1:
By merging the clock-activated transistor functionality into a single shared component, the patent reduces the total transistor count and associated parasitic effects. This consolidation minimizes voltage drops in the clock network and power supply, as fewer transistor gates are switching simultaneously, thereby reducing harmful voltage fluctuations while preserving data sampling capability.
3Reliability
If conventional latch architectures are used, then data storage is achieved, but internal node toggling occurs when input is constant
Solution Approach 1:
The patent implements periodic clocked operation where latches are enabled and disabled in sequence based on clock phases. During idle periods when data input is constant, the latches are clock-disabled, preventing internal node toggling. This periodic activation only when needed reduces unnecessary switching activity and energy loss from internal node transitions during stable input conditions.
4Use of energy by moving object
If shared clock-activated transistors are used, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent segments the latch bank into groups that share common clock-activated transistors, with each group managed by dedicated keeper subcircuits. This segmentation approach organizes the complexity into manageable units while achieving power reduction through sharing. The modular structure with clear segmentation between groups balances the increased architectural complexity with significant power consumption benefits.
Data Source
AI summary
Circuits, methods, and systems for generating data outputs based on sampled data inputs. One circuit includes a first latch including a first logic gate, a second logic gate, and a first keeper subcircuit. The circuit further includes a second latch including a third logic gate, a fourth logic gate, and a second keeper subcircuit. The first keeper subcircuit being electrically coupled via a first shared node of the first latch and the second latch, and the second keeper subcircuit being electrically coupled via a second shared node of the first latch and the second latch.