Shared Column Path Control Circuit for DRAM Bank Groups
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Solution Overview
Problem
As the clock frequency of semiconductor memory devices increases, the area occupied by column path control circuits in DRAMs grows proportionally with the number of bank groups, limiting data processing speed and efficiency due to the need for separate timing margins between bank groups within a limited tCCD.
Innovation Solution
A shared column path control circuit is implemented, which generates preliminary and main column pulses based on command signals and bank group addresses, allowing for synchronized access across multiple bank groups while minimizing redundant circuitry, thus reducing the overall area occupied by peripheral circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate column path control circuits are provided for each bank group, then reliable access control to each bank group is achieved, but the area occupied by peripheral circuits increases proportionally with the number of bank groups
Solution Approach 1:
The patent merges the column path control functionality across multiple bank groups into a single shared column path control circuit. This circuit can simultaneously control column paths for multiple bank groups by receiving bank group address signals and generating appropriate column selection signals for each bank group, thereby reducing the total circuit area while maintaining reliable access control to each bank group
Solution Approach 2:
The shared column path control circuit is designed with multi-functionality to handle access control for multiple bank groups. It receives bank group address signals and can generate column selection signals for different bank groups within the same circuit, making a single circuit perform the function of multiple separate circuits would have performed
2Productivity
If the clock frequency is increased to improve data processing speed, then productivity increases, but the area occupied by column path control circuits grows proportionally with the number of bank groups
Solution Approach 1:
The patent combines column path control functionality for multiple bank groups into a single shared circuit, preventing the peripheral circuit area from growing proportionally with the number of bank groups. This enables higher clock frequencies and improved data processing speed without the area penalty that would otherwise accompany increased bank group counts
3Reliability
If timing margins are maintained between bank groups within limited tCCD, then reliable operation is ensured, but data processing speed is limited
Solution Approach 1:
The shared column path control circuit performs preliminary processing of bank group address signals and command signals to generate column selection signals in advance. By proactively managing the timing and generation of control signals for multiple bank groups, the circuit ensures reliable operation within the limited tCCD window while maximizing data processing speed through efficient signal coordination
Data Source
AI summary
A semiconductor memory device may include a core circuit including a plurality of memory cell arrays electrically connected between a plurality of row lines and a plurality of column lines, and a column path control circuit configured to generate a preliminary column pulse from a command signal irrelevant to a column address signal, to generate a main column pulse in response to an enable time point of the column address signal and an enable time point of the preliminary column pulse, and to enable an access target column line among the plurality of column lines.