Shared Column Select Signals for Memory Element Density
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Solution Overview
Problem
As the number of memory cells in computing devices increases, the number of control signals required to access them also increases, leading to decreased density and larger memory element sizes due to routing requirements, which complicates the design and increases costs.
Innovation Solution
The implementation of a memory element design where each column of memory cells shares a common column select signal for both writing and reading, reducing the total number of column select signals needed and thereby minimizing the area required for routing these signals, thus enhancing density and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cells increases, then the storage capacity is improved, but the number of control signals increases leading to decreased density and larger memory element size
Solution Approach 1:
The patent combines write column select signals and read column select signals into shared column select signals. Multiple memory cell columns share common column select signal lines, reducing the total number of control signal lines required. This merging approach allows increased memory cell density without proportionally increasing the area dedicated to control signal routing.
Solution Approach 2:
The column select signal lines serve multiple functions by being shared between write operations and read operations. The same signal infrastructure is used for both writing data to memory cells and reading data from memory cells, eliminating the need for separate dedicated signal lines for each function and reducing overall signal line count.
2Adaptability or versatility
If separate write and read column select signals are used for each column, then the control functionality is improved, but the routing complexity and area increase
Solution Approach 1:
The patent merges write column select signals and read column select signals into shared column select signals that are commonly routed to multiple memory cell columns. This consolidation reduces routing complexity while maintaining the ability to selectively access columns for both write and read operations through the shared signal infrastructure.
Solution Approach 2:
The shared column select signal lines perform multiple functions by supporting both write operations and read operations. The same physical signal lines are used universally for different control purposes, reducing the overall complexity of the signal routing network while preserving full control functionality.
Data Source
AI summary
Apparatus are provided for memory elements and related computing modules. An exemplary memory element includes a first array of one or more memory cells, a second array of one or more memory cells, write selection circuitry associated with the first array, and read selection circuitry associated with the second array. The write selection circuitry and the read selection circuitry are configured to be activated concurrently.