Shared Comparator Architecture for Multi-Photodiode Image Sensors
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Solution Overview
Problem
Existing image pickup apparatus configurations require an analog-to-digital converter per photodiode, leading to a complex pixel configuration.
Innovation Solution
A comparator with a comparison section that can select and compare multiple analog signals with a reference signal, allowing a single analog-to-digital converter to be used across multiple photodiodes, simplifying the pixel configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If an analog-to-digital converter is arranged in each pixel for every photodiode, then analog-to-digital conversion can be performed simultaneously for all pixels, but the pixel configuration becomes complex
Solution Approach 1:
The comparator is designed with a selection section that can select from multiple analog signals (from different photodiodes) and a single comparison section that serves all photodiodes. This allows one comparator to perform the function of multiple comparators, reducing the number of components needed in each pixel while maintaining simultaneous conversion capability across all pixels.
2Device complexity
If a single comparator is shared among multiple photodiodes, then device complexity is reduced, but the comparator must handle multiple signals sequentially
Solution Approach 1:
The selection section rapidly cycles through multiple photodiode signals in a periodic manner, selecting each signal for comparison with the reference signal. This periodic switching allows the single comparator to process multiple signals in sequence while maintaining high conversion speed, as the switching occurs faster than the comparison time required.
Data Source
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AI summary
A comparator of an analog-to-digital converter is simplified. In the comparator, an input signal is input to a control terminal of each of a plurality of signal input transistors. The reference input transistor configures, together with each of the plurality of signal input transistors, a differential pair and has a control terminal to which a reference signal is input. A signal input transistor selection section selects any one of the plurality of signal input transistors, and generates a current in response to a difference between the input signal and the reference signal to flow in the differential pair configured with the selected signal input transistor and the reference input transistor. A load section converts, at a time of a change of a current flowing in any one of the plurality of signal input transistors and the reference input transistor in response to the difference, the change of the current into a change of a voltage, and outputs the change of the voltage as a result of comparison between the input signal and the reference signal.