Shared-Comparator RSD ADC for Accurate Double Sampling
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Solution Overview
Problem
Existing redundant signed digit (RSD) analog-to-digital converters (ADCs) face challenges in reducing surface area requirements on integrated circuits and maintaining conversion accuracy due to the need for multiple comparators and the disturbance of stored charge on capacitors during comparison.
Innovation Solution
A cyclic RSD ADC design that uses a single set of comparators shared between two sampling circuits, employing non-overlapping sampling clock signals to perform comparisons during non-overlapping time periods, thereby avoiding disturbance of stored charge and reducing surface area requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two sets of comparators are used in a double-sampled RSD stage, then conversion accuracy is maintained, but surface area on integrated circuit increases significantly
Solution Approach 1:
The patent merges the functionality of two separate comparator sets into a single shared comparator set. The same comparators are used in both sampling phases by resetting them between phases, thereby reducing the total surface area required on the integrated circuit while maintaining the double-sampled conversion capability.
Solution Approach 2:
The patent applies the discarding and recovering principle by resetting the comparators between sampling phases. The comparators are used in the first phase, then discarded (reset to initial state), and recovered for use in the second phase. This allows a single comparator set to serve multiple purposes across different time periods.
2Area of stationary object
If a single set of comparators is shared between two sampling circuits, then surface area is reduced, but a sampling clock at two times the ADC clock rate is required
Solution Approach 1:
The patent employs periodic action by using non-overlapping clock phases to alternately activate the single comparator set for each sampling phase. The comparators are activated in a periodic manner - first for phase one, then reset and activated again for phase two - allowing the same hardware to operate at the original clock rate through time-division multiplexing.
3Ease of operation
If comparators are activated during sampling phase, then comparison function is performed, but stored charge on sampling capacitors is disturbed reducing conversion accuracy
Solution Approach 1:
The patent segments the operational timeline into distinct non-overlapping phases: sampling phases where capacitors store charge, and comparison phases where comparators are activated. This temporal segmentation ensures that comparison operations occur only when capacitors are not actively sampling, preventing charge disturbance and maintaining conversion accuracy.
Solution Approach 2:
The patent applies preliminary action by completing the sampling and charge storage on capacitors before activating the comparators. The sampling phase is fully completed and capacitors are stable with their stored charge before the comparison phase begins, ensuring that comparator activation does not disturb the stored charge.
Data Source
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AI summary
An analog to digital converter (20) includes a first sample circuit (52) that samples an analog input during a first phase of a clock. A second sample circuit (54) samples the analog input during a second phase of the clock. A comparator (34) compares a reference to the output of the first sample circuit during a non-overlapping time between an end of the first phase and beginning of the second phase and compares the reference to the output of the second sample circuit during a non-overlapping time between an end of the second phase and beginning of the first phase. The first sample circuit (52) couples the sample of the analog input taken by the first sample circuit (52) to the input of the comparator (34) during the non-overlapping time between the end of the first phase and the beginning of the second phase and the second sample circuit (54) couples the sample of the analog input taken by the second sample circuit to the input of the comparator (34) during the non-overlapping time between the end of the second phase and the beginning of the first phase.