Shared Comparing Circuit for Content Addressable Memory Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Content addressable memories (CAMs) face challenges in reducing power consumption and occupation area, particularly in network equipment, due to their high cost, large cell size, and increasing power consumption with capacity, which hinders performance improvements in high-speed network applications.
Innovation Solution
A CAM design where a comparing/logic processing circuit is shared among multiple entries, reducing the number of mask cells and eliminating the need for match lines and search lines for each entry, thereby decreasing power consumption and occupation area while maintaining high-speed search operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a match detecting circuit is provided in each memory cell to enable high-speed parallel comparison, then search speed is improved, but occupation area and power consumption increase
Solution Approach 1:
The patent merges the match detecting circuit into a shared comparing/logic processing circuit that serves multiple memory cells. Instead of having dedicated match detecting circuits in each memory cell, the invention combines these functions into a centralized circuit that processes matches for multiple cells simultaneously, thereby reducing the total occupation area while maintaining high-speed parallel comparison capabilities.
Solution Approach 2:
The comparing/logic processing circuit performs multiple functions: it acts as a match detecting circuit for multiple memory cells, a logic processing unit for evaluating match conditions, and a comparison unit for evaluating comparison conditions. This multi-functionality eliminates the need for separate dedicated circuits for each memory cell, reducing overall occupation area while preserving high-speed search performance.
2Productivity
If match detecting circuits are provided for each memory cell to achieve simultaneous parallel comparison, then search performance is improved, but power consumption increases
Solution Approach 1:
The patent combines multiple match detecting functions into a single shared comparing/logic processing circuit. This consolidation reduces the total number of active circuits from one per memory cell to a single shared circuit, thereby significantly reducing power consumption while maintaining the ability to perform simultaneous parallel comparisons across multiple memory cells.
Solution Approach 2:
The shared comparing/logic processing circuit universally serves multiple memory cells by evaluating both match conditions and comparison conditions in a unified manner. This multi-functional approach allows the circuit to handle all comparison operations for multiple cells without requiring separate dedicated circuits, thus reducing overall power consumption while maintaining high search performance.
3Quantity of substance
If the CAM capacity is increased to store more network addresses, then address search capability is improved, but power consumption increases
Solution Approach 1:
The patent applies the merging principle at the circuit level, where a single shared comparing/logic processing circuit serves all memory cells regardless of CAM capacity. This means that increasing CAM capacity to store more network addresses does not require proportionally increasing the number of match detecting circuits, thereby decoupling capacity expansion from power consumption increase.
4Speed
If dedicated search lines and match lines are provided for each entry to enable high-speed comparison, then comparison speed is improved, but occupation area and power consumption increase
Solution Approach 1:
The patent merges the functions of dedicated search lines and match lines into a shared comparing/logic processing circuit. Instead of having separate physical lines for each entry, the invention uses a unified circuit architecture that processes comparison operations for multiple entries through shared signal paths, thereby reducing power consumption while maintaining high comparison speed.
Data Source
AI summary
The present invention is directed to reduce array area and power consumption in a content addressable memory. A comparator for performing a match determination and a size determination is provided commonly for plural entries each storing data to be retrieved. Each entry includes data storage cells for storing data and mask cells for storing mask bits. The number of mask cells is smaller than that of the data storage cells. Search data is transmitted to the comparator via a search data bus. One of the entries is selected according to a predetermined rule. The comparator decodes the mask bits, generates a mask instruction signal, and performs match comparison and size comparison between the search data and data to be retrieved which is stored in the selected entry.