Shared FinFET Contact Plug Structure to Prevent Gate Overetch

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Solution Overview

Problem

The double etching process for forming shared contacts in semiconductor devices can damage gate structures due to overetching, which affects the performance and reliability of electronic devices.

Innovation Solution

A semiconductor device design that includes a shared contact plug with a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connecting the two, along with a plug spacer film made of a different material from the insulating layer, which prevents overetching by maintaining the initial profile during the etching process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a double etching process is used to form shared contacts, then the shared contact structure can be formed to connect gate electrode to source/drain, but the gate structures (sidewall spacers) in the double-etched area are damaged

Engineering Contradiction:
Improveshared contact formationVSAvoidgate structure integrity
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The shared contact formation process is segmented into two separate single-etching processes: first etching the source/drain contact hole, then etching the gate contact hole. This segmentation avoids the double etching damage to sidewall spacers while still achieving the shared contact structure that connects both the source/drain region and gate electrode.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The source/drain contact hole is etched first before forming the gate contact hole. This preliminary action allows the sidewall spacers to be formed and protected before the second etching process, preventing damage to the gate structures during contact formation.

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If shared contacts are formed using conventional processes, then device integration is achieved, but overetching damages occur to sidewall spacers

Engineering Contradiction:
Improvedevice integrationVSAvoidsidewall spacer protection
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

A bulkhead structure is introduced as an intermediary element between the source/drain contact hole and gate contact hole. This bulkhead acts as a physical barrier and etch stop layer, preventing overetching from the second etching process from damaging the sidewall spacers of the gate structure, while still allowing the shared contact to function.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If double etching is performed to create shared contacts, then contact connectivity is established, but overetching areas cause structural damage

Engineering Contradiction:
Improvecontact connectivityVSAvoidoveretching damage
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The potential harmful effect of overetching is converted into a benefit by using the bulkhead structure as an etch stop. The bulkhead is specifically designed to be etched at a controlled rate, allowing the etching process to proceed safely without damaging the sidewall spacers, thus converting the overetching risk into a protective mechanism.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS11901422B2Semiconductor device having fin-type active patterns with shared contact plugs
Publication Date: 2024.02.13 SAMSUNG ELECTRONICS CO LTD
  • US11901422B2 patent drawing
  • US11901422B2 patent drawing
  • US11901422B2 patent drawing

AI summary

A semiconductor device includes a source/drain region in a fin-type active pattern, a gate structure adjacent to the source/drain region, and an insulating layer on the source/drain region and the gate structure. A shared contact plug penetrates through the insulating layer and includes a first lower portion connected to the source/drain region, a second lower portion connected to the gate structure, and an upper portion connected to upper surfaces of the first lower portion and the second lower portion. A plug spacer film is between the insulating layer and at least one of the first lower portion and the second lower portion and includes a material different from a material of the insulating layer.