Shared Source/Drain Contact Plug for Adjacent FinFET Isolation
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Solution Overview
Problem
As the semiconductor industry continues to reduce minimum feature sizes to increase integration density, new challenges arise in the manufacturing of FinFETs, including the need for precise control of material deposition and etching processes to maintain device performance and reliability.
Innovation Solution
The manufacturing process for FinFETs involves the formation of fins on a semiconductor substrate, followed by the deposition and patterning of insulating and conductive layers. This includes the use of advanced techniques such as epitaxial growth, chemical mechanical polishing, and the application of high-density plasma chemical vapor deposition to achieve the desired structural and electrical properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and control of material deposition and etching processes become more difficult
Solution Approach 1:
The patent segments the etching process into multiple distinct stages: a first etching process to form initial FinFET structures, and a second etching process to form additional features. This segmentation allows each etching step to be independently optimized and controlled, addressing the manufacturing precision challenges that arise when reducing minimum feature sizes for higher integration density.
Solution Approach 2:
The patent applies preliminary action by forming a mandrel structure and performing the first etching process to create FinFET structures before attempting to form additional features. This preliminary structuring establishes a foundation that enables subsequent precise patterning and material deposition, thereby maintaining manufacturing precision even as integration density increases.
2Reliability
If advanced techniques such as epitaxial growth and chemical mechanical polishing are used to maintain device performance, then reliability is improved, but device complexity and manufacturing process difficulty increase
Solution Approach 1:
The patent introduces an intermediary mandrel structure that facilitates the formation of FinFET devices. This mandrel serves as a temporary structure that enables precise control during the manufacturing process, allowing advanced techniques like epitaxial growth and chemical mechanical polishing to be applied more effectively. The mandrel acts as a mediator that simplifies the overall process complexity while maintaining device reliability.
Solution Approach 2:
The patent utilizes three-dimensional FinFET structures grown through epitaxial processes, transitioning from planar to vertical current flow. This dimensional change enables better control of device performance and reliability through enhanced gate control, while the structured approach to forming these 3D features helps manage the associated manufacturing complexity.
3Productivity
If etching processes are used to form FinFET structures, then device integration is achieved, but etching damage to source/drain regions occurs
Solution Approach 1:
The patent applies preliminary anti-action by carefully controlling the etching parameters and sequence to prevent damage to source/drain regions before it occurs. The first etching process is specifically designed to form FinFET structures while minimizing collateral damage, and subsequent processes are tailored to repair or mitigate any damage that does occur, thereby enabling device integration without excessive etching damage.
Solution Approach 2:
The patent converts the potentially harmful etching process into a beneficial tool by using controlled etching to define precise FinFET structures. The etching process, when properly managed, removes material to create the desired three-dimensional structures while the damage is minimized through selective etching and subsequent repair processes, thereby achieving device integration with acceptable damage levels.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The described manufacturing process enables the production of FinFETs with improved performance and reliability, allowing for the integration of more complex electronic components in a smaller area while minimizing etching damage and maintaining the dimensions and shape of the source/drain regions.
Implementation Method 1
the application of high-density plasma chemical vapor deposition to achieve the desired structural and electrical properties
Implementation Method 2
This includes the use of advanced techniques such as epitaxial growth
Implementation Method 3
chemical mechanical polishing
Data Source
AI summary
A semiconductor device and methods of forming the semiconductor device are described herein and are directed towards forming a source/drain contact plug for adjacent finFETs. The source/drain regions of the adjacent finFETs are embedded in an interlayer dielectric and are separated by an isolation region of a cut-metal gate (CMG) structure isolating gate electrodes of the adjacent finFETs The methods include recessing the isolation region, forming a contact plug opening through the interlayer dielectric to expose portions of a contact etch stop layer disposed over the source/drain regions through the contact plug opening, the contact etch stop layer being a different material from the material of the isolation region. Once exposed, the portions of the CESL are removed and a conductive material is formed in the contact plug opening and in contact with the source/drain regions of the adjacent finFETs and in contact with the isolation region.