Shared S/D Contacts Extending Into Channel Layers for Short-Channel Control
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Solution Overview
Problem
The scaling of features in integrated circuits (ICs) leads to short-channel effects such as poor leakage and subthreshold swing, which are exacerbated by reduced gate lengths, necessitating innovative transistor designs that optimize contact performance without increasing footprint.
Innovation Solution
Extending at least one source/drain (S/D) contact into a channel layer, while keeping it separated from the gate stack by a channel material, allows for a shorter effective gate length, reducing short-channel effects and improving contact resistance, especially at low temperatures where transistors can operate with shorter gate lengths without compromising performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate length is reduced to increase transistor density, then transistor density is improved, but short-channel effects worsen
Solution Approach 1:
The S/D contact extends vertically into the channel layer along the depth dimension rather than only laterally, transforming a 2D contact geometry into a 3D structure. This vertical extension into the channel layer reduces the effective gate length and mitigates short-channel effects while maintaining a compact lateral footprint for high transistor density
2Reliability
If S/D contact extends into channel layer, then contact resistance is improved, but device complexity increases
Solution Approach 1:
The S/D contact structure merges with the channel layer by extending into it, creating an integrated contact-channel interface. This merging increases the contact area and improves electrical contact resistance while the shared material interface simplifies the overall device structure compared to separate contact and channel components
Data Source
AI summary
The scaling of features in ICs has been a driving force behind an ever-growing semiconductor industry. As transistors of the ICs become smaller, their gate lengths become smaller, leading to undesirable short-channel effects such as poor leakage, poor subthreshold swing, drain-induced barrier lowering, etc. Embodiments of the present disclosure are based on recognition that extending at least one of two S/D contacts of a transistor into a channel layer while keeping it separated from a corresponding gate stack by a channel material may allow keeping the footprint of the transistor relatively small while effectively increasing transistor's effective gate length and thus reducing the negative impacts of short-channel effects. This architecture may be optimized even further if transistors are to be operated at relatively low temperatures, e.g., below 200 Kelvin degrees or lower. For multiple transistors, some of the S/D contacts may be shared to further increase transistor density.