Shared Control Gate Memory Cell Design for Disturbance Suppression
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Solution Overview
Problem
Semiconductor devices with two transistors face large cell size issues, while those with a single transistor suffer from low reliability due to disturbance during reading operations.
Innovation Solution
A semiconductor device design where two memory cells share a selection transistor and a control gate, with the memory transistors sharing impurity regions and source lines, allowing for compact cell size and reduced disturbance during reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two transistors are used per memory cell (selection transistor and memory transistor), then reliability is improved by suppressing disturbance during reading operations, but cell size increases
Solution Approach 1:
The patent merges the selection transistor and memory transistor into a single integrated structure where the selection transistor's source/drain region serves dual purposes: as the source/drain for the selection transistor itself and as the control gate for the memory transistor. This merging eliminates the need for separate transistors while maintaining the reliability benefits of the two-transistor architecture.
Solution Approach 2:
The selection transistor is designed to perform multiple functions simultaneously: it acts as the selection transistor for the memory cell and also serves as the control gate for the memory transistor. This multi-functionality reduces the total component count and cell size while preserving the disturbance suppression capability.
2Area of stationary object
If only one transistor is used per memory cell, then cell size is reduced, but reliability deteriorates due to disturbance during reading operations
Solution Approach 1:
The patent combines the selection and memory functions into a single transistor structure where the selection transistor's source/drain region simultaneously serves as the control gate for the memory transistor. This integration achieves compact cell size while maintaining reliability through the inherent disturbance suppression of the two-transistor architecture.
Solution Approach 2:
The single selection transistor is designed with multi-functionality, serving both as the selection transistor and as the control gate for the memory transistor. This universal design enables the cell to achieve small size while preserving the reliability benefits normally requiring two separate transistors.
3Reliability
If two transistors are used per memory cell, then disturbance during reading operations is suppressed, but device complexity increases
Solution Approach 1:
The patent merges two separate transistor structures into one integrated selection transistor that simultaneously functions as the selection device and the control gate. This merging reduces device complexity by eliminating redundant components while maintaining the disturbance suppression capability through the preserved two-transistor operational principle.
Solution Approach 2:
The selection transistor is designed with universal functionality to serve dual roles: as the selection transistor and as the control gate for the memory transistor. This multi-functionality simplifies the overall device structure and reduces complexity while maintaining reliable disturbance suppression during reading operations.
Data Source
AI summary
A semiconductor device in which the cell size is small and disturbance in reading operation is suppressed, and a method for manufacturing the semiconductor device. A first memory cell has a first memory transistor. A second memory cell has a second memory transistor. A control gate is shared by the first memory cell and the second memory cell. In plan view, the control gate is sandwiched between a first memory gate of the first memory transistor and a second memory gate of the second memory transistor.