Shared-Control Multi-Bit Level Shifter Layout for ESD and Area
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Solution Overview
Problem
Existing multi-bit level shifters occupy significant chip area and do not efficiently address the antenna effect, leading to increased space requirements and reduced ESD performance.
Innovation Solution
A multi-bit level shifter design where all N latch circuits share a common control inverter, reducing the number of inverters and transistors required, and incorporating a layout that allows output signals to be pulled to supply voltage or ground to prevent floating, while also eliminating the antenna effect and optimizing chip area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If each latch circuit uses its own control inverter, then each latch can be independently controlled, but the chip area increases significantly
Solution Approach 1:
Multiple latch circuits share a common control inverter to generate the reverse control signal, reducing the total number of inverters from N to 1. This merging of control resources significantly reduces chip area while maintaining functional operation of all latches through the shared inverted control signal.
Solution Approach 2:
The single control inverter serves multiple latch circuits simultaneously, making it a universal control element. This multi-functional approach allows one inverter to perform the control signal inversion function for N different latches, eliminating the need for N separate inverters and reducing overall circuit complexity and area.
2Device complexity
If output signals are left floating, then circuit complexity is reduced, but ESD performance deteriorates
Solution Approach 1:
The circuit proactively pulls output signals to defined voltage levels (supply voltage or ground) before potential ESD events can occur. By pre-establishing defined voltage states through pull-up or pull-down mechanisms, the circuit prevents floating conditions that would otherwise make it vulnerable to ESD damage, thereby improving reliability without adding complex protection circuits.
3Area of stationary object
If antenna effect is not addressed, then chip area is minimized, but ESD performance is compromised
Solution Approach 1:
The design extracts and removes the antenna effect from the circuit by implementing a layout that prevents charge accumulation on metal interconnects. By taking out the harmful antenna effect through strategic placement of transistors and routing, the circuit achieves both area efficiency and improved ESD performance without requiring additional large-area protection structures.
4Adaptability or versatility
If N inverters are used for N latch circuits, then each latch has dedicated control, but (N-1) inverters can be eliminated through sharing
Solution Approach 1:
N latch circuits share a single control inverter, merging the control function into one universal element. This reduces the quantity of inverters from N to 1 while maintaining the adaptability of each latch to respond to control signals, achieving both area reduction and functional versatility.
Data Source
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AI summary
A circuit includes a control inverter, a first latch circuit, and a second latch circuit. The control inverter receives a control signal to generate a reverse control signal. The first latch circuit is activated by the reverse control signal to convert a first input signal ranging from the first supply voltage to the ground into a first output signal ranging from the second supply voltage to the ground. The second latch circuit is activated by the reverse control signal to convert a second input signal ranging from a first supply voltage to the ground into a second output signal ranging from the second supply voltage to the ground. The first supply voltage and the second supply voltage are different.