Shared Co-Processor Micro-Architecture for Low-Power SoC Scheduling
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Solution Overview
Problem
Existing processor micro-architectures in low-power-consumption intelligent terminals face inefficiencies due to inflexible MCU selection, suboptimal multi-processor core architectures, and inability to extend instructions based on customer requirements, leading to performance issues and resource wastage.
Innovation Solution
A processor micro-architecture with a co-processor and multiple main processors connected via a request processing unit, allowing flexible configuration and shared resource utilization, supported by a RISC-V open source instruction set for customizable instruction sets and power management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional ARM MCU architecture is used for multiple main processors, then design simplicity and co-processor extension capability are improved, but BUS transmission delay increases and execution efficiency decreases
Solution Approach 1:
The patent segments the connection architecture by replacing the traditional shared BUS with dedicated connection channels between each main processor and the co-processor. This segmentation eliminates BUS contention and transmission delays while maintaining design simplicity through modular connection structures.
Solution Approach 2:
The patent introduces a bridge circuit as an intermediary component that enables direct communication between main processors and the co-processor without relying on the traditional BUS. This intermediary structure resolves the contradiction by providing efficient data transmission paths while preserving architectural simplicity.
2Reliability
If ARM MCU architecture with dedicated DSP co-processor for each core is used, then each processor has independent processing capability, but DSP resource sharing cannot be realized and resources are wasted
Solution Approach 1:
The patent merges multiple DSP co-processors into a single shared co-processor resource that can be accessed by multiple main processors. This consolidation eliminates resource duplication and waste while maintaining independent processing capability through controlled access mechanisms.
Solution Approach 2:
The patent creates a universal co-processor that can serve multiple main processors for different processing tasks. This multi-functional design allows the same hardware resource to be dynamically allocated to different processors based on computational needs, preventing resource waste while preserving processing independence.
3Ease of operation
If traditional ARM-based MCU is used, then general instruction processing is achieved, but instruction set cannot be extended according to customer requirements
Solution Approach 1:
The patent implements a dynamic instruction set architecture based on RISC-V that allows flexible configuration and extension of instructions according to specific application requirements. This dynamic design enables the system to adapt to different customer needs while maintaining ease of operation through a standardized base instruction set.
Solution Approach 2:
The patent enables instruction set parameter changes and customization through the RISC-V architecture, allowing the instruction set to be modified and extended to match specific application requirements. This parameter flexibility resolves the contradiction by maintaining general processing capability while enabling custom instruction sets.
4Adaptability or versatility
If multiple MCUs are integrated to achieve complex functions, then functional completeness is improved, but system complexity and power consumption increase
Solution Approach 1:
The patent merges multiple separate MCU functions into a unified system architecture with multiple main processors sharing common resources including memory, I/O interfaces, and the co-processor. This consolidation reduces system complexity while maintaining functional completeness through resource sharing.
Solution Approach 2:
The patent creates universal shared resources that can be accessed by multiple main processors to perform different functions. This multi-functional approach reduces the need for duplicate hardware components while maintaining the ability to implement complex functions across different processors.
Data Source
AI summary
Disclosed in the present invention are a processor micro-architecture, an SoC chip and a low-power-consumption intelligent device. The processor micro-architecture comprises a co-processor and at least two main processors, wherein each main processor is connected to the co-processor by means of a request processing unit; the request processing unit is used for determining, when a usage request that is initiated by the two main processors has been received, a processing sequence for the main processors that initiate the request, and generating and sending a feedback instruction to different main processors according to the processing sequence; and the main processor is used for sending a processing instruction to the co-processor for processing when the feedback instruction represents that usage is allowed. A plurality of main controllers access the same co-processor in a shared manner, thereby satisfying an instruction-level delay, and achieving the optimum balance between performance and power consumption.