Shared-Counter Timer Array for Low-Noise Timed Triggers
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Solution Overview
Problem
Prior art timer arrays in RF circuits suffer from high power consumption, digital noise, and layout inefficiencies due to a large number of counters, which increase dynamic power consumption and affect timing precision and consistency.
Innovation Solution
A timer array using a single reference counter with a count translation logic block to generate timed triggers, reducing the number of counters and enabling seamless integration into existing digital circuits while maintaining backward compatibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a timer array with multiple counters is used to generate timed triggers, then the ability to synchronize events is improved, but power consumption increases due to the large number of counters
Solution Approach 1:
The patent merges multiple independent counters into a single shared counter resource. Instead of having N separate counters for N timers, a single counter is shared among all timers, with each timer represented by a target register storing its deadline value. This consolidation dramatically reduces the number of active counting elements, thereby reducing dynamic power consumption while maintaining the ability to generate multiple timed triggers.
Solution Approach 2:
The single shared counter serves multiple functions by being reused across all timer operations. The counter is programmed sequentially with different target values from target registers, allowing it to generate multiple different timed triggers over time. This multi-functional approach eliminates the need for dedicated counters for each timer, reducing overall power consumption.
2Reliability
If a timer array with multiple counters is used to generate timed triggers, then the ability to synchronize events is improved, but digital noise increases due to the large number of counters
Solution Approach 1:
By merging multiple counters into a single shared counter, the patent reduces the total number of switching elements in the circuit. Fewer counters mean fewer simultaneous switching operations, which directly reduces digital noise generation. The single counter is activated sequentially for different timer operations rather than multiple counters operating simultaneously, thereby minimizing noise while preserving event synchronization capability.
3Reliability
If a timer array with multiple counters is used to generate timed triggers, then the ability to synchronize events is improved, but layout efficiency deteriorates due to the large number of counters
Solution Approach 1:
The patent consolidates N separate counter structures into a single counter structure, dramatically reducing the physical die area required. Instead of allocating space for N independent counters, the layout only needs to accommodate one counter plus N target registers (which are more compact than full counter structures). This merging approach significantly improves layout efficiency and reduces overall circuit area while maintaining full timer functionality.
4Reliability
If a timer array with multiple counters is used to generate timed triggers, then the ability to synchronize events is improved, but timing precision deteriorates due to the large number of counters
Solution Approach 1:
By using a single shared counter, the patent ensures uniform timing precision across all timers. The counter operates with consistent clocking and control logic, eliminating variations that might arise from having multiple independent counters with potentially different characteristics. The shared counter is programmed with precise target values from target registers, ensuring accurate and consistent timing for all synchronized events.
Data Source
AI summary
Methods and apparatuses for an optimal timer array using a single reference counter are presented. According to one aspect, timers of the timer array use the single reference counter to process different timed trigger requests. A count translation logic block translates counts corresponding to the requested timed triggers to target values of the reference counter. Register arrays that include the target values and active/inactive status flags of the timers are used to implement specific timers. Comparators are used to compare values of the reference counter to the target values to establish expiration of the requested timed triggers. A target translation logic block translates a current value of the reference counter to an offset value from the target values for monitoring by an external circuit.