Shared-Counter Watchdog Circuit for Multi-Process Timeout Monitoring
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Solution Overview
Problem
Existing watchdog circuits require separate counters for each process, leading to a large chip area and increased costs when monitoring a large number of processes.
Innovation Solution
A watchdog circuit with a common counter and memory elements for multiple processes, using a periodic signal with a fixed time interval longer than the longest planned process duration, to monitor and detect timeouts efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate counter is configured for each process to monitor timeout, then the reliability of process monitoring is improved, but the chip area and device complexity increase significantly
Solution Approach 1:
The patent merges multiple separate counter functions into a single shared counter resource. The counter is time-multiplexed across multiple processes, where each process receives dedicated monitoring attention at different time intervals. This combining approach maintains monitoring reliability for each process while dramatically reducing the hardware resources required compared to having separate counters for each process.
Solution Approach 2:
The single counter is designed to serve multiple processes universally. By implementing a universal counter that can be dynamically allocated to different processes based on their timeout requirements, the system achieves the functionality of multiple dedicated counters using a single multi-functional component, thereby reducing chip area while maintaining monitoring capability for all processes.
2Reliability
If a separate counter is configured for each process, then accurate timeout detection is achieved, but the device complexity and manufacturing costs increase
Solution Approach 1:
The patent combines multiple counter instances into a single shared counter resource that is time-multiplexed across processes. This merging reduces device complexity by eliminating redundant counter hardware while maintaining accurate timeout detection through proper timing management and process scheduling.
Solution Approach 2:
The system implements periodic monitoring intervals where the single counter is sequentially allocated to different processes. By using periodic action with carefully designed time intervals, the system maintains accurate timeout detection for each process while using a single counter, thereby reducing circuit complexity compared to continuous simultaneous monitoring with multiple counters.
3Reliability
If multiple processes are monitored simultaneously with separate watchdogs, then operational reliability is maintained, but the number of hardware components increases
Solution Approach 1:
The patent merges the functionality of multiple watchdog hardware components into a single shared watchdog circuit. By implementing time-multiplexed monitoring where one watchdog circuit sequentially monitors multiple processes, the system maintains operational reliability for all processes while reducing the quantity of hardware components from N separate watchdogs to a single shared watchdog.
Solution Approach 2:
The watchdog circuit is designed with universal monitoring capability that can be dynamically assigned to different processes. This multi-functional design allows a single watchdog component to perform the role of multiple dedicated watchdogs, thereby maintaining reliability across all processes while minimizing the number of hardware components required.
Data Source
AI summary
A watchdog circuit for monitoring a plurality of processes. The watchdog circuit is configured to provide a periodic signal with an adjustable fixed time interval to a control circuit. The control circuit is configured to receive the periodic signal from the timer and use periodic signal to monitor the plurality of processes. Each of the plurality of processes has a planned process duration. The fixed time interval is set to be longer than the longest planned process duration of the plurality of planned process durations.